Loading arch/arm64/include/asm/mmu.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -18,6 +18,7 @@ #define USER_ASID_FLAG (UL(1) << 48) #define USER_ASID_FLAG (UL(1) << 48) #define TTBR_ASID_MASK (UL(0xffff) << 48) #ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__ Loading arch/arm64/include/asm/uaccess.h +4 −3 Original line number Original line Diff line number Diff line Loading @@ -20,6 +20,7 @@ #include <asm/alternative.h> #include <asm/alternative.h> #include <asm/kernel-pgtable.h> #include <asm/kernel-pgtable.h> #include <asm/mmu.h> #include <asm/sysreg.h> #include <asm/sysreg.h> #ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__ Loading Loading @@ -138,7 +139,7 @@ static inline void __uaccess_ttbr0_disable(void) write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); isb(); isb(); /* Set reserved ASID */ /* Set reserved ASID */ ttbr &= ~(0xffffUL << 48); ttbr &= ~TTBR_ASID_MASK; write_sysreg(ttbr, ttbr1_el1); write_sysreg(ttbr, ttbr1_el1); isb(); isb(); } } Loading @@ -157,7 +158,7 @@ static inline void __uaccess_ttbr0_enable(void) /* Restore active ASID */ /* Restore active ASID */ ttbr1 = read_sysreg(ttbr1_el1); ttbr1 = read_sysreg(ttbr1_el1); ttbr1 |= ttbr0 & (0xffffUL << 48); ttbr1 |= ttbr0 & TTBR_ASID_MASK; write_sysreg(ttbr1, ttbr1_el1); write_sysreg(ttbr1, ttbr1_el1); isb(); isb(); Loading Loading @@ -453,7 +454,7 @@ extern __must_check long strnlen_user(const char __user *str, long n); msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 isb isb sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE bic \tmp1, \tmp1, #(0xffff << 48) bic \tmp1, \tmp1, #TTBR_ASID_MASK msr ttbr1_el1, \tmp1 // set reserved ASID msr ttbr1_el1, \tmp1 // set reserved ASID isb isb .endm .endm Loading arch/arm64/kernel/entry.S +1 −1 Original line number Original line Diff line number Diff line Loading @@ -151,7 +151,7 @@ alternative_else_nop_endif .if \el != 0 .if \el != 0 mrs x21, ttbr1_el1 mrs x21, ttbr1_el1 tst x21, #0xffff << 48 // Check for the reserved ASID tst x21, #TTBR_ASID_MASK // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR Loading Loading
arch/arm64/include/asm/mmu.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -18,6 +18,7 @@ #define USER_ASID_FLAG (UL(1) << 48) #define USER_ASID_FLAG (UL(1) << 48) #define TTBR_ASID_MASK (UL(0xffff) << 48) #ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__ Loading
arch/arm64/include/asm/uaccess.h +4 −3 Original line number Original line Diff line number Diff line Loading @@ -20,6 +20,7 @@ #include <asm/alternative.h> #include <asm/alternative.h> #include <asm/kernel-pgtable.h> #include <asm/kernel-pgtable.h> #include <asm/mmu.h> #include <asm/sysreg.h> #include <asm/sysreg.h> #ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__ Loading Loading @@ -138,7 +139,7 @@ static inline void __uaccess_ttbr0_disable(void) write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); isb(); isb(); /* Set reserved ASID */ /* Set reserved ASID */ ttbr &= ~(0xffffUL << 48); ttbr &= ~TTBR_ASID_MASK; write_sysreg(ttbr, ttbr1_el1); write_sysreg(ttbr, ttbr1_el1); isb(); isb(); } } Loading @@ -157,7 +158,7 @@ static inline void __uaccess_ttbr0_enable(void) /* Restore active ASID */ /* Restore active ASID */ ttbr1 = read_sysreg(ttbr1_el1); ttbr1 = read_sysreg(ttbr1_el1); ttbr1 |= ttbr0 & (0xffffUL << 48); ttbr1 |= ttbr0 & TTBR_ASID_MASK; write_sysreg(ttbr1, ttbr1_el1); write_sysreg(ttbr1, ttbr1_el1); isb(); isb(); Loading Loading @@ -453,7 +454,7 @@ extern __must_check long strnlen_user(const char __user *str, long n); msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 isb isb sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE bic \tmp1, \tmp1, #(0xffff << 48) bic \tmp1, \tmp1, #TTBR_ASID_MASK msr ttbr1_el1, \tmp1 // set reserved ASID msr ttbr1_el1, \tmp1 // set reserved ASID isb isb .endm .endm Loading
arch/arm64/kernel/entry.S +1 −1 Original line number Original line Diff line number Diff line Loading @@ -151,7 +151,7 @@ alternative_else_nop_endif .if \el != 0 .if \el != 0 mrs x21, ttbr1_el1 mrs x21, ttbr1_el1 tst x21, #0xffff << 48 // Check for the reserved ASID tst x21, #TTBR_ASID_MASK // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR Loading