Loading drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c +6 −6 Original line number Diff line number Diff line Loading @@ -1241,7 +1241,7 @@ static struct clk_regmap_div dsi1pll_post_bit_div = { static struct clk_regmap_mux dsi0pll_byteclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_byteclk", Loading @@ -1255,7 +1255,7 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { static struct clk_regmap_mux dsi1pll_byteclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_byteclk", Loading @@ -1269,7 +1269,7 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { static struct clk_regmap_mux dsi0pll_pclk_src_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_pclk_src_mux", Loading @@ -1284,7 +1284,7 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = { static struct clk_regmap_mux dsi1pll_pclk_src_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_pclk_src_mux", Loading Loading @@ -1329,7 +1329,7 @@ static struct clk_regmap_div dsi1pll_pclk_src = { static struct clk_regmap_mux dsi0pll_pclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_dsiclk", Loading @@ -1343,7 +1343,7 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { static struct clk_regmap_mux dsi1pll_pclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_dsiclk", Loading Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c +6 −6 Original line number Diff line number Diff line Loading @@ -1241,7 +1241,7 @@ static struct clk_regmap_div dsi1pll_post_bit_div = { static struct clk_regmap_mux dsi0pll_byteclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_byteclk", Loading @@ -1255,7 +1255,7 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { static struct clk_regmap_mux dsi1pll_byteclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_byteclk", Loading @@ -1269,7 +1269,7 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { static struct clk_regmap_mux dsi0pll_pclk_src_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_pclk_src_mux", Loading @@ -1284,7 +1284,7 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = { static struct clk_regmap_mux dsi1pll_pclk_src_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_pclk_src_mux", Loading Loading @@ -1329,7 +1329,7 @@ static struct clk_regmap_div dsi1pll_pclk_src = { static struct clk_regmap_mux dsi0pll_pclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_dsiclk", Loading @@ -1343,7 +1343,7 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { static struct clk_regmap_mux dsi1pll_pclk_mux = { .shift = 0, .width = 0, .width = 1, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_dsiclk", Loading