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Commit 45aef0b9 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
Browse files

drivers: clk: qcom: Modify width to overcome out of bounds errors 



Modify width of fixed mux from zero to one to overcome out of
bounds errors.

Change-Id: I807e3439ae5c667b2d0575f31c6907da6bdef56e
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 7fc1bbb1

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+6 −6
Original line number Diff line number Diff line
@@ -1219,7 +1219,7 @@ static struct clk_regmap_div dsi1pll_post_bit_div = { 


static struct clk_regmap_mux dsi0pll_byteclk_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0_phy_pll_out_byteclk",
@@ -1233,7 +1233,7 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { 


static struct clk_regmap_mux dsi1pll_byteclk_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1_phy_pll_out_byteclk",
@@ -1247,7 +1247,7 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { 


static struct clk_regmap_mux dsi0pll_pclk_src_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_pclk_src_mux",
@@ -1262,7 +1262,7 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = { 


static struct clk_regmap_mux dsi1pll_pclk_src_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_pclk_src_mux",
@@ -1307,7 +1307,7 @@ static struct clk_regmap_div dsi1pll_pclk_src = { 


static struct clk_regmap_mux dsi0pll_pclk_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0_phy_pll_out_dsiclk",
@@ -1321,7 +1321,7 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { 


static struct clk_regmap_mux dsi1pll_pclk_mux = {

	.shift = 0,

	.width = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1_phy_pll_out_dsiclk",