drm/msm/dsi-staging: fix dsi clock calculation for low bpp

Dsi clocks were calculated with fixed 24 bits per pxel.
Fix it to update the clocks as per panel bpp.

CRs-Fixed: 2249576
Change-Id: I00c3b892755685d4decf4933409775581a00ee34
Signed-off-by: Vara Reddy <varar@codeaurora.org>