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Commit 32216c93 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: correct scale offset for some gamut modes"

parents b7da490c c057d9d3

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+3 −3
Original line number Diff line number Diff line
@@ -13,10 +13,10 @@ 
#define _SDE_HW_COLOR_PROC_COMMON_V4_H_



#define GAMUT_TABLE_SEL_OFF 0x4

#define GAMUT_SCALEA_OFFSET_OFF 0x10

#define GAMUT_SCALEB_OFFSET_OFF 0x50

#define GAMUT_LOWER_COLOR_OFF 0xc

#define GAMUT_UPPER_COLOR_OFF 0x8

#define GAMUT_LOWER_COLOR_OFF 0xc

#define GAMUT_SCALEA_OFFSET_OFF 0x10

#define GAMUT_SCALEB_OFFSET_OFF 0xe0

#define GAMUT_TABLE0_SEL BIT(12)

#define GAMUT_MAP_EN BIT(1)

#define GAMUT_EN BIT(0)

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.c

+14 −7
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw, 
		u32 *opcode)

{

	u32 reg, tbl_len, tbl_off, scale_off, i, j;

	u32 scale_tbl_len, scale_tbl_off;

	u32 *scale_data;



	if (!payload || !opcode || !hw) {
@@ -50,7 +51,7 @@ static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw, 
		*opcode = gamut_mode_5 << 2;

		*opcode |= GAMUT_MAP_EN;

		tbl_len = GAMUT_3D_MODE5_TBL_SZ;

		tbl_off = 0;

		tbl_off = GAMUT_MODE_5_OFF;

		scale_off = GAMUT_SCALEB_OFFSET_OFF;

		break;

	default:
@@ -75,12 +76,18 @@ static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw, 
	}



	if ((*opcode & GAMUT_MAP_EN)) {

		scale_data = &payload->scale_off[0][0];

		tbl_off = base + scale_off;

		tbl_len = GAMUT_3D_SCALE_OFF_TBL_NUM * GAMUT_3D_SCALE_OFF_SZ;

		for (i = 0; i < tbl_len; i++)

			SDE_REG_WRITE(hw, tbl_off + (i * sizeof(u32)),

					scale_data[i]);

		if (scale_off == GAMUT_SCALEA_OFFSET_OFF)

			scale_tbl_len = GAMUT_3D_SCALE_OFF_SZ;

		else

			scale_tbl_len = GAMUT_3D_SCALEB_OFF_SZ;

		for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {

			scale_tbl_off = base + scale_off + i * scale_tbl_len;

			scale_data = &payload->scale_off[i][0];

			for (j = 0; j < scale_tbl_len; j++)

				SDE_REG_WRITE(hw,

					scale_tbl_off + (j * sizeof(u32)),

					scale_data[j]);

		}

	}

	SDE_REG_WRITE(hw, base, *opcode);

	return 0;

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+21 −8
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
		REG_DMA_HEADERS_BUFFER_SZ)

#define GAMUT_SCALE_OFF_LEN (GAMUT_3D_SCALE_OFF_SZ * \

		GAMUT_3D_SCALE_OFF_TBL_NUM * sizeof(u32))

#define GAMUT_SCALE_OFF_LEN_12 (GAMUT_3D_SCALEB_OFF_SZ * sizeof(u32))



#define GC_LUT_MEM_SIZE ((sizeof(struct drm_msm_pgc_lut)) + \

		REG_DMA_HEADERS_BUFFER_SZ)
@@ -430,6 +431,8 @@ void reg_dmav1_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg) 
	struct sde_reg_dma_kickoff_cfg kick_off;

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	u32 op_mode, reg, tbl_len, tbl_off, scale_off, i;

	u32 scale_tbl_len, scale_tbl_off;

	u32 *scale_data;

	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;

	struct sde_hw_reg_dma_ops *dma_ops;

	int rc;
@@ -493,16 +496,26 @@ void reg_dmav1_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg) 
	}



	if (op_mode & GAMUT_MAP_EN) {

		REG_DMA_SETUP_OPS(dma_write_cfg,

			ctx->cap->sblk->gamut.base + scale_off,

			payload->scale_off[0], GAMUT_SCALE_OFF_LEN,

		if (scale_off == GAMUT_SCALEA_OFFSET_OFF)

			scale_tbl_len = GAMUT_SCALE_OFF_LEN;

		else

			scale_tbl_len = GAMUT_SCALE_OFF_LEN_12;



		for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {

			scale_tbl_off = ctx->cap->sblk->gamut.base + scale_off +

					(i * scale_tbl_len);

			scale_data = &payload->scale_off[i][0];

			REG_DMA_SETUP_OPS(dma_write_cfg, scale_tbl_off,

					scale_data, scale_tbl_len,

					REG_BLK_WRITE_SINGLE, 0, 0);

			rc = dma_ops->setup_payload(&dma_write_cfg);

			if (rc) {

			DRM_ERROR("write scale/off reg failed ret %d\n", rc);

				DRM_ERROR("write scale/off reg failed ret %d\n",

						rc);

				return;

			}

		}

	}



	REG_DMA_SETUP_OPS(dma_write_cfg,

		ctx->cap->sblk->gamut.base,

include/uapi/drm/msm_drm_pp.h

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ struct drm_msm_memcol { 
#define GAMUT_3D_MODE5_TBL_SZ 32

#define GAMUT_3D_MODE13_TBL_SZ 550

#define GAMUT_3D_SCALE_OFF_SZ 16

#define GAMUT_3D_SCALEB_OFF_SZ 12

#define GAMUT_3D_TBL_NUM 4

#define GAMUT_3D_SCALE_OFF_TBL_NUM 3

#define GAMUT_3D_MAP_EN (1 << 0)