Commit 2e274768 authored Feb 09, 2016 by Florian Fainelli Committed by Ralf Baechle May 13, 2016

MIPS: Move RIXI exception enabling after vendor-specific cpu_probe



Some processors may not have the RIXI bit advertised in the Config3 register,
not being a MIPS32R2 or R6 core, yet, they might be supporting it through a
different way, which is overriden during vendor-specific cpu_probe().

Move the RIXI exceptions enabling after the vendor-specific cpu_probe()
function has had a change to run and override the current CPU's options with
MIPS_CPU_RIXI.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: pgynther@google.com
Cc: paul.burton@imgtec.com
Cc: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12506/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 8256b17e

arch/mips/kernel/cpu-probe.c

+9 −9

Original line number	Diff line number	Diff line
		@@ -862,15 +862,6 @@ static void decode_configs(struct cpuinfo_mips *c)

		mips_probe_watch_registers(c);

		if (cpu_has_rixi) {
		/* Enable the RIXI exceptions */
		set_c0_pagegrain(PG_IEC);
		back_to_back_c0_hazard();
		/* Verify the IEC bit is set */
		if (read_c0_pagegrain() & PG_IEC)
		c->options \|= MIPS_CPU_RIXIEX;
		}

		#ifndef CONFIG_MIPS_CPS
		if (cpu_has_mips_r2_r6) {
		c->core = get_ebase_cpunum();
		@@ -1733,6 +1724,15 @@ void cpu_probe(void)
		*/
		BUG_ON(current_cpu_type() != c->cputype);

		if (cpu_has_rixi) {
		/* Enable the RIXI exceptions */
		set_c0_pagegrain(PG_IEC);
		back_to_back_c0_hazard();
		/* Verify the IEC bit is set */
		if (read_c0_pagegrain() & PG_IEC)
		c->options \|= MIPS_CPU_RIXIEX;
		}

		if (mips_fpu_disabled)
		c->options &= ~MIPS_CPU_FPU;