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Commit 8256b17e authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle
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MIPS: Allow RIXI to be used on non-R2 or R6 cores 



Some processors, like Broadcom's BMIPS4380 and BMIPS5000 support RIXI and the
"rotr" instruction, which can be used to get a slightly more efficient page
table layout.

Introduce a CONFIG_CPU_HAS_RIXI such that those cores can benefit from this
feature. Perform the conditional check updates where relevant.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: pgynther@google.com
Cc: paul.burton@imgtec.com
Cc: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12505/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e56c7e18

arch/mips/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -1996,11 +1996,13 @@ config CPU_MIPSR1 
config CPU_MIPSR2

	bool

	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON

	select CPU_HAS_RIXI

	select MIPS_SPRAM



config CPU_MIPSR6

	bool

	default y if CPU_MIPS32_R6 || CPU_MIPS64_R6

	select CPU_HAS_RIXI

	select HAVE_ARCH_BITREVERSE

	select MIPS_ASID_BITS_VARIABLE

	select MIPS_SPRAM
@@ -2421,6 +2423,9 @@ config CPU_HAS_WB 
config XKS01

	bool



config CPU_HAS_RIXI

	bool



#

# Vectored interrupt mode is an R2 feature

#

arch/mips/include/asm/pgtable-bits.h

+4 −4
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ enum pgtable_bits { 
enum pgtable_bits {

	/* Used only by software (masked out before writing EntryLo*) */

	_PAGE_PRESENT_SHIFT,

#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6)

#if !defined(CONFIG_CPU_HAS_RIXI)

	_PAGE_NO_READ_SHIFT,

#endif

	_PAGE_WRITE_SHIFT,
@@ -115,7 +115,7 @@ enum pgtable_bits { 
#endif



	/* Used by TLB hardware (placed in EntryLo*) */

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

#if defined(CONFIG_CPU_HAS_RIXI)

	_PAGE_NO_EXEC_SHIFT,

	_PAGE_NO_READ_SHIFT,

#endif
@@ -139,7 +139,7 @@ enum pgtable_bits { 
/* Used by TLB hardware (placed in EntryLo*) */

#if defined(CONFIG_XPA)

# define _PAGE_NO_EXEC		(1 << _PAGE_NO_EXEC_SHIFT)

#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

#elif defined(CONFIG_CPU_HAS_RIXI)

# define _PAGE_NO_EXEC		(cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)

#endif

#define _PAGE_NO_READ		(1 << _PAGE_NO_READ_SHIFT)
@@ -180,7 +180,7 @@ enum pgtable_bits { 
 */

static inline uint64_t pte_to_entrylo(unsigned long pte_val)

{

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

#ifdef CONFIG_CPU_HAS_RIXI

	if (cpu_has_rixi) {

		int sa;

#ifdef CONFIG_32BIT