Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 285924ae authored by AnilKumar Chimata's avatar AnilKumar Chimata
Browse files

ARM: dts: msm: Add crypto device nodes for sdm845 



Add crypto device nodes with the required configuration
on the include file, which is needed to initialize the
the crypto drivers for sdm845 to perform crypto related
operations.

Change-Id: I93480e6b94d6f1ebcb9e988c5204615d7e2fb852
Signed-off-by: default avatarAnilKumar Chimata <anilc@codeaurora.org>
parent 2e81590b

arch/arm64/boot/dts/qcom/sdm845.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -2172,6 +2172,65 @@ 
		hyplog-size-offset = <0x414>;

	};



	qcom_cedev: qcedev@1de0000 {

		compatible = "qcom,qcedev";

		reg = <0x1de0000 0x20000>,

			<0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 272 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,bam-ee = <0>;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<125 512 0 0>,

				<125 512 393600 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc GCC_CE1_CLK>,

			 <&clock_gcc GCC_CE1_CLK>,

			 <&clock_gcc GCC_CE1_AHB_CLK>,

			 <&clock_gcc GCC_CE1_AXI_CLK>;

		qcom,ce-opp-freq = <171430000>;

	};



	qcom_crypto: qcrypto@1de0000 {

		compatible = "qcom,qcrypto";

		reg = <0x1de0000 0x20000>,

			 <0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 272 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,bam-ee = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<125 512 0 0>,

			<125 512 393600 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc GCC_CE1_CLK>,

			 <&clock_gcc GCC_CE1_CLK>,

			 <&clock_gcc GCC_CE1_AHB_CLK>,

			 <&clock_gcc GCC_CE1_AXI_CLK>;

		qcom,ce-opp-freq = <171430000>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-aead-algo;

		qcom,use-sw-hmac-algo;

	};



	qcom,msm_gsi {

		compatible = "qcom,msm_gsi";

	};