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Commit 2e81590b authored by AnilKumar Chimata's avatar AnilKumar Chimata
Browse files

ARM: dts: msm: Add ICE device node for sdm845 



Add ICE device node with the required configuration on
the include file, which is needed to initialize the ICE
driver for sdm845 to perform crypto related operations.

Change-Id: I4192f6042834095a180d046c200a69db3eaee6fe
Signed-off-by: default avatarAnilKumar Chimata <anilc@codeaurora.org>
parent c6d522c5

arch/arm64/boot/dts/qcom/sdm845.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -1021,6 +1021,29 @@ 
		mbox-names = "qdss_clk";

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";
@@ -1044,6 +1067,7 @@ 
		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */