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Commit 24e02ba7 authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: option to specify Root Complex max link speed 



Provide an option to specify Root Complex max link speed
capability to determine which configuration to use for
PCIe core.

Change-Id: Ic9d8474520d2f665a1556049a2bf0ae9ad13be14
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 41e63ece

Documentation/devicetree/bindings/pci/msm_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ Optional Properties: 
  - qcom,common-clk-en: Enables the common clock configuration for the endpoint.

  - qcom,clk-power-manage-en: Enables the clock power management for the

    endpoint.

  - qcom,max-link-speed: Max Gen speed Root complex supports.

  - qcom,n-fts: The number of fast training sequences sent when the link state

    is changed from L0s to L0.

  - qcom,pcie-phy-ver: version of PCIe PHY.
@@ -256,6 +257,7 @@ Example: 
		qcom,l1-supported;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;

		qcom,max-link-speed = <0x2>;

		qcom,n-fts = <0x50>;

		qcom,pcie-phy-ver = <1>;

		qcom,boot-option = <0x1>;

drivers/pci/host/pci-msm.c

+14 −0
Original line number Diff line number Diff line
@@ -147,6 +147,10 @@ 
#define LINKDOWN_WAITING_US_MAX	   5100

#define LINKDOWN_WAITING_COUNT	    200



#define GEN1_SPEED 0x1

#define GEN2_SPEED 0x2

#define GEN3_SPEED 0x3



#define PHY_READY_TIMEOUT_COUNT		   10

#define XMLH_LINK_UP				  0x400

#define MAX_LINK_RETRIES 5
@@ -477,6 +481,7 @@ struct msm_pcie_dev_t { 
	bool				smmu_exist;

	uint32_t			smmu_sid_base;

	uint32_t			   n_fts;

	uint32_t			max_link_speed;

	bool				 ext_ref_clk;

	uint32_t			   ep_latency;

	uint32_t			wr_halt_size;
@@ -1125,6 +1130,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->linkdown_counter);

	PCIE_DBG_FS(dev, "wake_counter: %lu\n",

		dev->wake_counter);

	PCIE_DBG_FS(dev, "max_link_speed: 0x%x\n",

		dev->max_link_speed);

	PCIE_DBG_FS(dev, "link_turned_on_counter: %lu\n",

		dev->link_turned_on_counter);

	PCIE_DBG_FS(dev, "link_turned_off_counter: %lu\n",
@@ -5277,6 +5284,13 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n",

				msm_pcie_dev[rc_idx].n_fts);



	msm_pcie_dev[rc_idx].max_link_speed = GEN2_SPEED;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,max-link-speed",

				&msm_pcie_dev[rc_idx].max_link_speed);

	PCIE_DBG(&msm_pcie_dev[rc_idx], "PCIe: RC%d: max-link-speed: 0x%x.\n",

		rc_idx, msm_pcie_dev[rc_idx].max_link_speed);



	msm_pcie_dev[rc_idx].ext_ref_clk =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,ext-ref-clk");