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Commit 41e63ece authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: add option to change slave address space size 



Each Root Complex has different address space size. Provide
an option to change slave address space size register.

Change-Id: I85bc2ef14b19db2da2a215c119ac5c9c5a2af5d5
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 010ff9e0

Documentation/devicetree/bindings/pci/msm_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ Optional Properties: 
    stable after power on, before de-assert the PERST to the endpoint.

  - qcom,wr-halt-size: With base 2, this exponent determines the size of the

    data that PCIe core will halt on for each write transaction.

  - qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.

  - qcom,cpl-timeout: Completion timeout value. This value specifies the time range

    which the root complex will send out a completion packet if there is no response

    from the endpoint.
@@ -266,6 +267,7 @@ Example: 
		qcom,smmu-sid-base = <0x1480>;

		qcom,ep-latency = <100>;

		qcom,wr-halt-size = <0xa>; /* 1KB */

		qcom,slv-addr-space-size = <0x1000000>; /* 16MB */

		qcom,cpl-timeout = <0x2>;



		iommus = <&anoc0_smmu>;

drivers/pci/host/pci-msm.c

+13 −9
Original line number Diff line number Diff line
@@ -480,6 +480,7 @@ struct msm_pcie_dev_t { 
	bool				 ext_ref_clk;

	uint32_t			   ep_latency;

	uint32_t			wr_halt_size;

	uint32_t			slv_addr_space_size;

	uint32_t			cpl_timeout;

	uint32_t			current_bdf;

	uint32_t			perst_delay_us_min;
@@ -1096,6 +1097,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->ep_latency);

	PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",

		dev->wr_halt_size);

	PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",

		dev->slv_addr_space_size);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",

		dev->cpl_timeout);

	PCIE_DBG_FS(dev, "current_bdf: 0x%x\n",
@@ -3652,14 +3655,7 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
			readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));

	}



	if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_16M)

		writel_relaxed(SZ_32M, dev->parf +

			PCIE20_PARF_SLV_ADDR_SPACE_SIZE);

	else if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M)

		writel_relaxed(SZ_16M, dev->parf +

			PCIE20_PARF_SLV_ADDR_SPACE_SIZE);

	else

		writel_relaxed(SZ_8M, dev->parf +

	writel_relaxed(dev->slv_addr_space_size, dev->parf +

		PCIE20_PARF_SLV_ADDR_SPACE_SIZE);



	if (dev->use_msi) {
@@ -5311,6 +5307,14 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: wr-halt-size: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].wr_halt_size);



	msm_pcie_dev[rc_idx].slv_addr_space_size = SZ_16M;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,slv-addr-space-size",

				&msm_pcie_dev[rc_idx].slv_addr_space_size);

	PCIE_DBG(&msm_pcie_dev[rc_idx],

		"RC%d: slv-addr-space-size: 0x%x.\n",

		rc_idx, msm_pcie_dev[rc_idx].slv_addr_space_size);



	msm_pcie_dev[rc_idx].cpl_timeout = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,cpl-timeout",