Loading Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt +14 −0 Original line number Diff line number Diff line Loading @@ -323,6 +323,20 @@ First Level Node - FG Gen3 device discharging. If not specified, a value of 0 will be set. Allowed range is from 245 to 62256. - qcom,ki-coeff-low-dischg Usage: optional Value type: <u32> Definition: Ki coefficient value for low discharge current during discharging. Value has no unit. Allowed range is 0-62200 in micro units. - qcom,ki-coeff-hi-chg Usage: optional Value type: <u32> Definition: Ki coefficient value for high charge current during charging. Value has no unit. Allowed range is 0-62200 in micro units. - qcom,fg-rconn-mohms Usage: optional Value type: <u32> Loading drivers/power/supply/qcom/fg-core.h +4 −0 Original line number Diff line number Diff line Loading @@ -182,8 +182,10 @@ enum fg_sram_param_id { FG_SRAM_DELTA_BSOC_THR, FG_SRAM_RECHARGE_SOC_THR, FG_SRAM_RECHARGE_VBATT_THR, FG_SRAM_KI_COEFF_LOW_DISCHG, FG_SRAM_KI_COEFF_MED_DISCHG, FG_SRAM_KI_COEFF_HI_DISCHG, FG_SRAM_KI_COEFF_HI_CHG, FG_SRAM_KI_COEFF_FULL_SOC, FG_SRAM_ESR_TIGHT_FILTER, FG_SRAM_ESR_BROAD_FILTER, Loading Loading @@ -299,6 +301,8 @@ struct fg_dt_props { int esr_meas_curr_ma; int bmd_en_delay_ms; int ki_coeff_full_soc_dischg; int ki_coeff_low_dischg; int ki_coeff_hi_chg; int jeita_thresholds[NUM_JEITA_LEVELS]; int ki_coeff_soc[KI_COEFF_SOC_LEVELS]; int ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS]; Loading drivers/power/supply/qcom/qpnp-fg-gen3.c +47 −0 Original line number Diff line number Diff line Loading @@ -128,6 +128,8 @@ #define KI_COEFF_MED_DISCHG_v2_OFFSET 0 #define KI_COEFF_HI_DISCHG_v2_WORD 10 #define KI_COEFF_HI_DISCHG_v2_OFFSET 1 #define KI_COEFF_HI_CHG_v2_WORD 11 #define KI_COEFF_HI_CHG_v2_OFFSET 2 #define DELTA_BSOC_THR_v2_WORD 12 #define DELTA_BSOC_THR_v2_OFFSET 3 #define DELTA_MSOC_THR_v2_WORD 13 Loading Loading @@ -312,12 +314,18 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = { ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL), PARAM(ESR_PULSE_THRESH, ESR_PULSE_THRESH_WORD, ESR_PULSE_THRESH_OFFSET, 1, 100000, 390625, 0, fg_encode_default, NULL), PARAM(KI_COEFF_LOW_DISCHG, KI_COEFF_LOW_DISCHG_v2_WORD, KI_COEFF_LOW_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_MED_DISCHG, KI_COEFF_MED_DISCHG_v2_WORD, KI_COEFF_MED_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_v2_WORD, KI_COEFF_HI_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_HI_CHG, KI_COEFF_HI_CHG_v2_WORD, KI_COEFF_HI_CHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_FULL_SOC, KI_COEFF_FULL_SOC_WORD, KI_COEFF_FULL_SOC_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), Loading Loading @@ -4221,6 +4229,35 @@ static int fg_hw_init(struct fg_chip *chip) } } if (chip->dt.ki_coeff_low_dischg != -EINVAL) { fg_encode(chip->sp, FG_SRAM_KI_COEFF_LOW_DISCHG, chip->dt.ki_coeff_low_dischg, &val); rc = fg_sram_write(chip, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].addr_word, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].addr_byte, &val, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].len, FG_IMA_DEFAULT); if (rc < 0) { pr_err("Error in writing ki_coeff_low_dischg, rc=%d\n", rc); return rc; } } if (chip->dt.ki_coeff_hi_chg != -EINVAL) { fg_encode(chip->sp, FG_SRAM_KI_COEFF_HI_CHG, chip->dt.ki_coeff_hi_chg, &val); rc = fg_sram_write(chip, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].len, FG_IMA_DEFAULT); if (rc < 0) { pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc); return rc; } } return 0; } Loading Loading @@ -4683,6 +4720,16 @@ static int fg_parse_ki_coefficients(struct fg_chip *chip) if (!rc) chip->dt.ki_coeff_full_soc_dischg = temp; chip->dt.ki_coeff_hi_chg = -EINVAL; rc = of_property_read_u32(node, "qcom,ki-coeff-hi-chg", &temp); if (!rc) chip->dt.ki_coeff_hi_chg = temp; chip->dt.ki_coeff_low_dischg = -EINVAL; rc = of_property_read_u32(node, "qcom,ki-coeff-low-dischg", &temp); if (!rc) chip->dt.ki_coeff_low_dischg = temp; rc = fg_parse_dt_property_u32_array(node, "qcom,ki-coeff-soc-dischg", chip->dt.ki_coeff_soc, KI_COEFF_SOC_LEVELS); if (rc < 0) Loading Loading
Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt +14 −0 Original line number Diff line number Diff line Loading @@ -323,6 +323,20 @@ First Level Node - FG Gen3 device discharging. If not specified, a value of 0 will be set. Allowed range is from 245 to 62256. - qcom,ki-coeff-low-dischg Usage: optional Value type: <u32> Definition: Ki coefficient value for low discharge current during discharging. Value has no unit. Allowed range is 0-62200 in micro units. - qcom,ki-coeff-hi-chg Usage: optional Value type: <u32> Definition: Ki coefficient value for high charge current during charging. Value has no unit. Allowed range is 0-62200 in micro units. - qcom,fg-rconn-mohms Usage: optional Value type: <u32> Loading
drivers/power/supply/qcom/fg-core.h +4 −0 Original line number Diff line number Diff line Loading @@ -182,8 +182,10 @@ enum fg_sram_param_id { FG_SRAM_DELTA_BSOC_THR, FG_SRAM_RECHARGE_SOC_THR, FG_SRAM_RECHARGE_VBATT_THR, FG_SRAM_KI_COEFF_LOW_DISCHG, FG_SRAM_KI_COEFF_MED_DISCHG, FG_SRAM_KI_COEFF_HI_DISCHG, FG_SRAM_KI_COEFF_HI_CHG, FG_SRAM_KI_COEFF_FULL_SOC, FG_SRAM_ESR_TIGHT_FILTER, FG_SRAM_ESR_BROAD_FILTER, Loading Loading @@ -299,6 +301,8 @@ struct fg_dt_props { int esr_meas_curr_ma; int bmd_en_delay_ms; int ki_coeff_full_soc_dischg; int ki_coeff_low_dischg; int ki_coeff_hi_chg; int jeita_thresholds[NUM_JEITA_LEVELS]; int ki_coeff_soc[KI_COEFF_SOC_LEVELS]; int ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS]; Loading
drivers/power/supply/qcom/qpnp-fg-gen3.c +47 −0 Original line number Diff line number Diff line Loading @@ -128,6 +128,8 @@ #define KI_COEFF_MED_DISCHG_v2_OFFSET 0 #define KI_COEFF_HI_DISCHG_v2_WORD 10 #define KI_COEFF_HI_DISCHG_v2_OFFSET 1 #define KI_COEFF_HI_CHG_v2_WORD 11 #define KI_COEFF_HI_CHG_v2_OFFSET 2 #define DELTA_BSOC_THR_v2_WORD 12 #define DELTA_BSOC_THR_v2_OFFSET 3 #define DELTA_MSOC_THR_v2_WORD 13 Loading Loading @@ -312,12 +314,18 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = { ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL), PARAM(ESR_PULSE_THRESH, ESR_PULSE_THRESH_WORD, ESR_PULSE_THRESH_OFFSET, 1, 100000, 390625, 0, fg_encode_default, NULL), PARAM(KI_COEFF_LOW_DISCHG, KI_COEFF_LOW_DISCHG_v2_WORD, KI_COEFF_LOW_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_MED_DISCHG, KI_COEFF_MED_DISCHG_v2_WORD, KI_COEFF_MED_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_v2_WORD, KI_COEFF_HI_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_HI_CHG, KI_COEFF_HI_CHG_v2_WORD, KI_COEFF_HI_CHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), PARAM(KI_COEFF_FULL_SOC, KI_COEFF_FULL_SOC_WORD, KI_COEFF_FULL_SOC_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), Loading Loading @@ -4221,6 +4229,35 @@ static int fg_hw_init(struct fg_chip *chip) } } if (chip->dt.ki_coeff_low_dischg != -EINVAL) { fg_encode(chip->sp, FG_SRAM_KI_COEFF_LOW_DISCHG, chip->dt.ki_coeff_low_dischg, &val); rc = fg_sram_write(chip, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].addr_word, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].addr_byte, &val, chip->sp[FG_SRAM_KI_COEFF_LOW_DISCHG].len, FG_IMA_DEFAULT); if (rc < 0) { pr_err("Error in writing ki_coeff_low_dischg, rc=%d\n", rc); return rc; } } if (chip->dt.ki_coeff_hi_chg != -EINVAL) { fg_encode(chip->sp, FG_SRAM_KI_COEFF_HI_CHG, chip->dt.ki_coeff_hi_chg, &val); rc = fg_sram_write(chip, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val, chip->sp[FG_SRAM_KI_COEFF_HI_CHG].len, FG_IMA_DEFAULT); if (rc < 0) { pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc); return rc; } } return 0; } Loading Loading @@ -4683,6 +4720,16 @@ static int fg_parse_ki_coefficients(struct fg_chip *chip) if (!rc) chip->dt.ki_coeff_full_soc_dischg = temp; chip->dt.ki_coeff_hi_chg = -EINVAL; rc = of_property_read_u32(node, "qcom,ki-coeff-hi-chg", &temp); if (!rc) chip->dt.ki_coeff_hi_chg = temp; chip->dt.ki_coeff_low_dischg = -EINVAL; rc = of_property_read_u32(node, "qcom,ki-coeff-low-dischg", &temp); if (!rc) chip->dt.ki_coeff_low_dischg = temp; rc = fg_parse_dt_property_u32_array(node, "qcom,ki-coeff-soc-dischg", chip->dt.ki_coeff_soc, KI_COEFF_SOC_LEVELS); if (rc < 0) Loading