Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 41 SUBLEVEL = 48 EXTRAVERSION = NAME = Roaring Lionus Loading arch/alpha/include/asm/types.h +1 −1 Original line number Diff line number Diff line #ifndef _ALPHA_TYPES_H #define _ALPHA_TYPES_H #include <asm-generic/int-ll64.h> #include <uapi/asm/types.h> #endif /* _ALPHA_TYPES_H */ arch/alpha/include/uapi/asm/types.h +11 −1 Original line number Diff line number Diff line Loading @@ -9,8 +9,18 @@ * need to be careful to avoid a name clashes. */ #ifndef __KERNEL__ /* * This is here because we used to use l64 for alpha * and we don't want to impact user mode with our change to ll64 * in the kernel. * * However, some user programs are fine with this. They can * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here. */ #if !defined(__SANE_USERSPACE_TYPES__) && !defined(__KERNEL__) #include <asm-generic/int-l64.h> #else #include <asm-generic/int-ll64.h> #endif #endif /* _UAPI_ALPHA_TYPES_H */ arch/arc/include/asm/cache.h +2 −0 Original line number Diff line number Diff line Loading @@ -89,7 +89,9 @@ extern unsigned long perip_base, perip_end; #define ARC_REG_SLC_FLUSH 0x904 #define ARC_REG_SLC_INVALIDATE 0x905 #define ARC_REG_SLC_RGN_START 0x914 #define ARC_REG_SLC_RGN_START1 0x915 #define ARC_REG_SLC_RGN_END 0x916 #define ARC_REG_SLC_RGN_END1 0x917 /* Bit val in SLC_CONTROL */ #define SLC_CTRL_IM 0x040 Loading arch/arc/mm/cache.c +11 −2 Original line number Diff line number Diff line Loading @@ -562,6 +562,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) static DEFINE_SPINLOCK(lock); unsigned long flags; unsigned int ctrl; phys_addr_t end; spin_lock_irqsave(&lock, flags); Loading Loading @@ -591,8 +592,16 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) * END needs to be setup before START (latter triggers the operation) * END can't be same as START, so add (l2_line_sz - 1) to sz */ write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); write_aux_reg(ARC_REG_SLC_RGN_START, paddr); end = paddr + sz + l2_line_sz - 1; if (is_pae40_enabled()) write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end)); write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end)); if (is_pae40_enabled()) write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr)); write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr)); while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 41 SUBLEVEL = 48 EXTRAVERSION = NAME = Roaring Lionus Loading
arch/alpha/include/asm/types.h +1 −1 Original line number Diff line number Diff line #ifndef _ALPHA_TYPES_H #define _ALPHA_TYPES_H #include <asm-generic/int-ll64.h> #include <uapi/asm/types.h> #endif /* _ALPHA_TYPES_H */
arch/alpha/include/uapi/asm/types.h +11 −1 Original line number Diff line number Diff line Loading @@ -9,8 +9,18 @@ * need to be careful to avoid a name clashes. */ #ifndef __KERNEL__ /* * This is here because we used to use l64 for alpha * and we don't want to impact user mode with our change to ll64 * in the kernel. * * However, some user programs are fine with this. They can * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here. */ #if !defined(__SANE_USERSPACE_TYPES__) && !defined(__KERNEL__) #include <asm-generic/int-l64.h> #else #include <asm-generic/int-ll64.h> #endif #endif /* _UAPI_ALPHA_TYPES_H */
arch/arc/include/asm/cache.h +2 −0 Original line number Diff line number Diff line Loading @@ -89,7 +89,9 @@ extern unsigned long perip_base, perip_end; #define ARC_REG_SLC_FLUSH 0x904 #define ARC_REG_SLC_INVALIDATE 0x905 #define ARC_REG_SLC_RGN_START 0x914 #define ARC_REG_SLC_RGN_START1 0x915 #define ARC_REG_SLC_RGN_END 0x916 #define ARC_REG_SLC_RGN_END1 0x917 /* Bit val in SLC_CONTROL */ #define SLC_CTRL_IM 0x040 Loading
arch/arc/mm/cache.c +11 −2 Original line number Diff line number Diff line Loading @@ -562,6 +562,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) static DEFINE_SPINLOCK(lock); unsigned long flags; unsigned int ctrl; phys_addr_t end; spin_lock_irqsave(&lock, flags); Loading Loading @@ -591,8 +592,16 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) * END needs to be setup before START (latter triggers the operation) * END can't be same as START, so add (l2_line_sz - 1) to sz */ write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); write_aux_reg(ARC_REG_SLC_RGN_START, paddr); end = paddr + sz + l2_line_sz - 1; if (is_pae40_enabled()) write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end)); write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end)); if (is_pae40_enabled()) write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr)); write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr)); while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); Loading