Merge "ARM: dts: msm: Add clk rates for ufs phy axi clock in sdhc1 in sdm670"

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

						192000000 384000000>;

		qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000

				100000000 200000000 200000000>;

		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;