Commit 01db23ae authored Nov 09, 2017 by Vijay Viswanath

ARM: dts: msm: Add clk rates for ufs phy axi clock in sdhc1 in sdm670



Ufs_phy_axi clock needs to be scaled when the sdcc1_apps clock is
scaled. So add the rates at which ufs_phy clock should run corresponding
to the rate of the sdcc1_apps clock.

Change-Id: I78fa1989dc4da92e32af5786a8a0530c2e92c60e
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>

parent c9e2c0f9

arch/arm64/boot/dts/qcom/sdm670.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -2206,6 +2206,8 @@

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
		192000000 384000000>;
		qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
		100000000 200000000 200000000>;
		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;