Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1f7247c0 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Add wrappers to handle fifo underrun interrupts 



Way too much copypasta all over. And this also clarifies a bit what's
going on since it separates the "do we have an underrun irq" from the
"should we report the underrun" check.

v2: Fix excessively long lines.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parent a72e4c9f

drivers/gpu/drm/i915/i915_irq.c

+21 −51
Original line number Diff line number Diff line
@@ -1796,10 +1796,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) 
		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

			i9xx_pipe_crc_irq_handler(dev, pipe);



		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

		    intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,

							  false))

			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

	}



	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
@@ -1966,16 +1964,10 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");



	if (pch_iir & SDE_TRANSA_FIFO_UNDER)

		if (intel_set_pch_fifo_underrun_reporting(dev_priv,

							  TRANSCODER_A,

							  false))

			DRM_ERROR("PCH transcoder A FIFO underrun\n");

		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);



	if (pch_iir & SDE_TRANSB_FIFO_UNDER)

		if (intel_set_pch_fifo_underrun_reporting(dev_priv,

							  TRANSCODER_B,

							  false))

			DRM_ERROR("PCH transcoder B FIFO underrun\n");

		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);

}



static void ivb_err_int_handler(struct drm_device *dev)
@@ -1988,12 +1980,8 @@ static void ivb_err_int_handler(struct drm_device *dev) 
		DRM_ERROR("Poison interrupt\n");



	for_each_pipe(dev_priv, pipe) {

		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {

			if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,

								  false))

				DRM_ERROR("Pipe %c FIFO underrun\n",

					  pipe_name(pipe));

		}

		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))

			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);



		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {

			if (IS_IVYBRIDGE(dev))
@@ -2015,19 +2003,13 @@ static void cpt_serr_int_handler(struct drm_device *dev) 
		DRM_ERROR("PCH poison interrupt\n");



	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,

							  false))

			DRM_ERROR("PCH transcoder A FIFO underrun\n");

		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);



	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,

							  false))

			DRM_ERROR("PCH transcoder B FIFO underrun\n");

		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);



	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,

							  false))

			DRM_ERROR("PCH transcoder C FIFO underrun\n");

		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);



	I915_WRITE(SERR_INT, serr_int);

}
@@ -2093,11 +2075,7 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 
			intel_check_page_flip(dev, pipe);



		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))

			if (intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe,

								  false))

				DRM_ERROR("Pipe %c FIFO underrun\n",

					  pipe_name(pipe));

			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);



		if (de_iir & DE_PIPE_CRC_DONE(pipe))

			i9xx_pipe_crc_irq_handler(dev, pipe);
@@ -2316,13 +2294,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) 
			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)

				hsw_pipe_crc_irq_handler(dev, pipe);



			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {

				if (intel_set_cpu_fifo_underrun_reporting(dev_priv,

									  pipe,

									  false))

					DRM_ERROR("Pipe %c FIFO underrun\n",

						  pipe_name(pipe));

			}

			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)

				intel_cpu_fifo_underrun_irq_handler(dev_priv,

								    pipe);





			if (IS_GEN9(dev))
@@ -3839,10 +3813,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) 
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

				intel_cpu_fifo_underrun_irq_handler(dev_priv,

								    pipe);

		}



		iir = new_iir;
@@ -4034,10 +4007,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) 
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

				intel_cpu_fifo_underrun_irq_handler(dev_priv,

								    pipe);

		}



		if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -4263,10 +4235,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) 
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

		}



		if (blc_event || (iir & I915_ASLE_INTERRUPT))

drivers/gpu/drm/i915/intel_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -761,6 +761,10 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum transcoder pch_transcoder,

					   bool enable);

void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum pipe pipe);

void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum transcoder pch_transcoder);

void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);

bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,

					   enum pipe pipe);

drivers/gpu/drm/i915/intel_fifo_underrun.c

+17 −0
Original line number Diff line number Diff line
@@ -308,3 +308,20 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return old;

}



void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum pipe pipe)

{

	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false))

		DRM_ERROR("CPU pipe %c FIFO underrun\n",

			  pipe_name(pipe));

}



void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum transcoder pch_transcoder)

{

	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,

						  false))

		DRM_ERROR("PCH transcoder %c FIFO underrun\n",

			  transcoder_name(pch_transcoder));

}