Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a72e4c9f authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Use dev_priv in public intel_fifo_underrun.c functions 



It's the new rule!

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 47339cd9

drivers/gpu/drm/i915/i915_irq.c

+22 −13
Original line number Diff line number Diff line
@@ -1750,7 +1750,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) 
		 * handle.

		 */

		mask = 0;

		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))

		if (__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe))

			mask |= PIPE_FIFO_UNDERRUN_STATUS;



		switch (pipe) {
@@ -1797,7 +1797,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) 
			i9xx_pipe_crc_irq_handler(dev, pipe);



		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

		    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))

		    intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,

							  false))

			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

	}
@@ -1965,12 +1966,14 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");



	if (pch_iir & SDE_TRANSA_FIFO_UNDER)

		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,

		if (intel_set_pch_fifo_underrun_reporting(dev_priv,

							  TRANSCODER_A,

							  false))

			DRM_ERROR("PCH transcoder A FIFO underrun\n");



	if (pch_iir & SDE_TRANSB_FIFO_UNDER)

		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,

		if (intel_set_pch_fifo_underrun_reporting(dev_priv,

							  TRANSCODER_B,

							  false))

			DRM_ERROR("PCH transcoder B FIFO underrun\n");

}
@@ -1986,7 +1989,7 @@ static void ivb_err_int_handler(struct drm_device *dev) 


	for_each_pipe(dev_priv, pipe) {

		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {

			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,

			if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,

								  false))

				DRM_ERROR("Pipe %c FIFO underrun\n",

					  pipe_name(pipe));
@@ -2012,17 +2015,17 @@ static void cpt_serr_int_handler(struct drm_device *dev) 
		DRM_ERROR("PCH poison interrupt\n");



	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,

							  false))

			DRM_ERROR("PCH transcoder A FIFO underrun\n");



	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,

							  false))

			DRM_ERROR("PCH transcoder B FIFO underrun\n");



	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)

		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,

		if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,

							  false))

			DRM_ERROR("PCH transcoder C FIFO underrun\n");
@@ -2090,7 +2093,9 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 
			intel_check_page_flip(dev, pipe);



		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))

			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))

			if (intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe,

								  false))

				DRM_ERROR("Pipe %c FIFO underrun\n",

					  pipe_name(pipe));
@@ -2312,7 +2317,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) 
				hsw_pipe_crc_irq_handler(dev, pipe);



			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {

				if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,

				if (intel_set_cpu_fifo_underrun_reporting(dev_priv,

									  pipe,

									  false))

					DRM_ERROR("Pipe %c FIFO underrun\n",

						  pipe_name(pipe));
@@ -3834,7 +3840,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) 
				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

		}
@@ -4028,7 +4035,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) 
				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

		}
@@ -4256,7 +4264,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) 
				i9xx_pipe_crc_irq_handler(dev, pipe);



			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&

			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))

			    intel_set_cpu_fifo_underrun_reporting(dev_priv,

								  pipe, false))

				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

		}

drivers/gpu/drm/i915/intel_display.c

+20 −15
Original line number Diff line number Diff line
@@ -4163,8 +4163,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 


	intel_crtc->active = true;



	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);

	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_enable)
@@ -4278,13 +4278,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) 


	intel_crtc->active = true;



	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_enable)

			encoder->pre_enable(encoder);



	if (intel_crtc->config.has_pch_encoder) {

		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,

						      true);

		dev_priv->display.fdi_link_train(crtc);

	}
@@ -4360,7 +4361,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
		encoder->disable(encoder);



	if (intel_crtc->config.has_pch_encoder)

		intel_set_pch_fifo_underrun_reporting(dev, pipe, false);

		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);



	intel_disable_pipe(intel_crtc);
@@ -4374,7 +4375,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
		ironlake_fdi_disable(crtc);



		ironlake_disable_pch_transcoder(dev_priv, pipe);

		intel_set_pch_fifo_underrun_reporting(dev, pipe, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);



		if (HAS_PCH_CPT(dev)) {

			/* disable TRANS_DP_CTL */
@@ -4427,7 +4428,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) 
	}



	if (intel_crtc->config.has_pch_encoder)

		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);

		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,

						      false);

	intel_disable_pipe(intel_crtc);



	if (intel_crtc->config.dp_encoder_is_mst)
@@ -4441,7 +4443,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) 


	if (intel_crtc->config.has_pch_encoder) {

		lpt_disable_pch_transcoder(dev_priv);

		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,

						      true);

		intel_ddi_fdi_disable(crtc);

	}
@@ -4818,6 +4821,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev) 
static void valleyview_crtc_enable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_encoder *encoder;

	int pipe = intel_crtc->pipe;
@@ -4846,7 +4850,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 


	intel_crtc->active = true;



	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_pll_enable)
@@ -4879,7 +4883,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc_enable_planes(crtc);



	/* Underruns don't raise interrupts, so check manually. */

	i9xx_check_fifo_underruns(dev);

	i9xx_check_fifo_underruns(dev_priv);

}



static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -4894,6 +4898,7 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 
static void i9xx_crtc_enable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_encoder *encoder;

	int pipe = intel_crtc->pipe;
@@ -4915,7 +4920,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc->active = true;



	if (!IS_GEN2(dev))

		intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_enable)
@@ -4946,10 +4951,10 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 
	 * but leave the pipe running.

	 */

	if (IS_GEN2(dev))

		intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);



	/* Underruns don't raise interrupts, so check manually. */

	i9xx_check_fifo_underruns(dev);

	i9xx_check_fifo_underruns(dev_priv);

}



static void i9xx_pfit_disable(struct intel_crtc *crtc)
@@ -4985,7 +4990,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) 
	 * but leave the pipe running.

	 */

	if (IS_GEN2(dev))

		intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);



	/*

	 * Vblank time updates from the shadow to live plane control register
@@ -5031,7 +5036,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) 
	}



	if (!IS_GEN2(dev))

		intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);



	intel_crtc->active = false;

	intel_update_watermarks(crtc);

drivers/gpu/drm/i915/intel_drv.h

+4 −4
Original line number Diff line number Diff line
@@ -756,13 +756,13 @@ static inline unsigned int intel_num_planes(struct intel_crtc *crtc) 
}



/* intel_fifo_underrun.c */

bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,

bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum pipe pipe, bool enable);

bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,

bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum transcoder pch_transcoder,

					   bool enable);

void i9xx_check_fifo_underruns(struct drm_device *dev);

bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,

void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);

bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,

					   enum pipe pipe);



/* i915_irq.c */

drivers/gpu/drm/i915/intel_fifo_underrun.c

+12 −13
Original line number Diff line number Diff line
@@ -64,14 +64,13 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev) 
	return true;

}



void i9xx_check_fifo_underruns(struct drm_device *dev)

void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *crtc;



	spin_lock_irq(&dev_priv->irq_lock);



	for_each_intel_crtc(dev, crtc) {

	for_each_intel_crtc(dev_priv->dev, crtc) {

		u32 reg = PIPESTAT(crtc->pipe);

		u32 pipestat;
@@ -239,24 +238,23 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 
	return old;

}



bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,

bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum pipe pipe, bool enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned long flags;

	bool ret;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);

	ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe,

						      enable);

	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);



	return ret;

}



bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,

bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,

					   enum pipe pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -277,11 +275,10 @@ bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, 
 *

 * Returns the previous state of underrun reporting.

 */

bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,

bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum transcoder pch_transcoder,

					   bool enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	unsigned long flags;
@@ -301,10 +298,12 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 
	old = !intel_crtc->pch_fifo_underrun_disabled;

	intel_crtc->pch_fifo_underrun_disabled = !enable;



	if (HAS_PCH_IBX(dev))

		ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);

	if (HAS_PCH_IBX(dev_priv->dev))

		ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,

						enable);

	else

		cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);

		cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,

						enable, old);



	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return old;