Loading arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h> #include <dt-bindings/msm/msm-bus-ids.h> &soc { /* USB port for DWC3 controller */ Loading Loading @@ -47,6 +48,19 @@ resets = <&clock_gcc GCC_USB30_BCR>; reset-names = "core_reset"; qcom,msm-bus,name = "usb"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>, <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 240000 700000>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>, <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h> #include <dt-bindings/msm/msm-bus-ids.h> &soc { /* USB port for DWC3 controller */ Loading Loading @@ -47,6 +48,19 @@ resets = <&clock_gcc GCC_USB30_BCR>; reset-names = "core_reset"; qcom,msm-bus,name = "usb"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>, <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 240000 700000>, <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>, <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; Loading