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Commit 1c607f0a authored Jul 28, 2014 by Arnd Bergmann

Merge tag 'v3.17-rockchip-rk3xxx-dts' of...

Merge tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "ARM: dts: changes for existing rockchip boards" from Heiko Stuebner:

Collected changes for existing Rockchip boards
- convert to new clock driver
- bring structure in line with recent rk3288 comments
  (no soc-nodes, using phandles when adding changes, sorted by address)
- i2c, board-pmic and pwm nodes nodes
- sd card slot and ir receiver on radxa rock

* tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: dts: rk3188-radxarock: add GPIO IR receiver node
  ARM: dts: rockchip: add pwm nodes
  ARM: dts: rockchip: add both clocks to uart nodes
  ARM: dts: rk3188-radxarock: enable sd-card slot
  ARM: dts: add i2c and regulator nodes to rk3188-radxarock
  ARM: dts: rockchip: add tps65910 regulator for bqcurie2
  ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings
  ARM: dts: rockchip: oder nodes by register address
  ARM: dts: rockchip: remove address from pinctrl nodes
  ARM: dts: uses handles to reference nodes for changes
  ARM: dts: rockchip: add handles for shared nodes that don't have one yet
  ARM: dts: rockchip: remove soc subnodes
  arm: dts: rockchip: remove obsolete clock gate definitions
  ARM: dts: rockchip: move oscillator input clock into main dtsi
  ARM: dts: rockchip: add cru nodes and update device clocks to use it

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parents b99cfa66 08567053

arch/arm/boot/dts/rk3066a-bqcurie2.dts

+145 −65

Original line number	Diff line number	Diff line
		@@ -24,40 +24,131 @@
		reg = <0x60000000 0x40000000>;
		};

		soc {
		uart0: serial@10124000 {
		status = "okay";
		vcc_sd0: fixed-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sdmmc-supply";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
		};

		uart1: serial@10126000 {
		status = "okay";
		gpio-keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		autorepeat;

		button@0 {
		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
		linux,code = <116>;
		label = "GPIO Key Power";
		linux,input-type = <1>;
		gpio-key,wakeup = <1>;
		debounce-interval = <100>;
		};
		button@1 {
		gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
		linux,code = <104>;
		label = "GPIO Key Vol-";
		linux,input-type = <1>;
		gpio-key,wakeup = <0>;
		debounce-interval = <100>;
		};
		/* VOL+ comes somehow thru the ADC */
		};
		};

		uart2: serial@20064000 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		&i2c1 {
		status = "okay";
		clock-frequency = <400000>;

		tps: tps@2d {
		reg = <0x2d>;

		interrupt-parent = <&gpio6>;
		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;

		vcc5-supply = <&vcc_io>;
		vcc6-supply = <&vcc_io>;

		regulators {
		vcc_rtc: regulator@0 {
		regulator-name = "vcc_rtc";
		regulator-always-on;
		};

		uart3: serial@20068000 {
		status = "okay";
		vcc_io: regulator@1 {
		regulator-name = "vcc_io";
		regulator-always-on;
		};

		vcc_sd0: fixed-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sdmmc-supply";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100000>;
		vdd_arm: regulator@2 {
		regulator-name = "vdd_arm";
		regulator-min-microvolt = <600000>;
		regulator-max-microvolt = <1500000>;
		regulator-boot-on;
		regulator-always-on;
		};

		vcc_ddr: regulator@3 {
		regulator-name = "vcc_ddr";
		regulator-min-microvolt = <600000>;
		regulator-max-microvolt = <1500000>;
		regulator-boot-on;
		regulator-always-on;
		};

		vcc18_cif: regulator@5 {
		regulator-name = "vcc18_cif";
		regulator-always-on;
		};

		dwmmc@10214000 { /* sdmmc */
		vdd_11: regulator@6 {
		regulator-name = "vdd_11";
		regulator-always-on;
		};

		vcc_25: regulator@7 {
		regulator-name = "vcc_25";
		regulator-always-on;
		};

		vcc_18: regulator@8 {
		regulator-name = "vcc_18";
		regulator-always-on;
		};

		vcc25_hdmi: regulator@9 {
		regulator-name = "vcc25_hdmi";
		regulator-always-on;
		};

		vcca_33: regulator@10 {
		regulator-name = "vcca_33";
		regulator-always-on;
		};

		vcc_tp: regulator@11 {
		regulator-name = "vcc_tp";
		regulator-always-on;
		};

		vcc28_cif: regulator@12 {
		regulator-name = "vcc28_cif";
		regulator-always-on;
		};
		};
		};
		};

		/* must be included after &tps gets defined */
		#include "tps65910.dtsi"

		&mmc0 { /* sdmmc */
		num-slots = <1>;
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
		vmmc-supply = <&vcc_sd0>;

		slot@0 {
		@@ -67,7 +158,7 @@
		};
		};

		dwmmc@10218000 { /* wifi */
		&mmc1 { /* wifi */
		num-slots = <1>;
		status = "okay";
		non-removable;
		@@ -82,29 +173,18 @@
		};
		};

		gpio-keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		autorepeat;

		button@0 {
		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
		linux,code = <116>;
		label = "GPIO Key Power";
		linux,input-type = <1>;
		gpio-key,wakeup = <1>;
		debounce-interval = <100>;
		};
		button@1 {
		gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
		linux,code = <104>;
		label = "GPIO Key Vol-";
		linux,input-type = <1>;
		gpio-key,wakeup = <0>;
		debounce-interval = <100>;
		&uart0 {
		status = "okay";
		};
		/* VOL+ comes somehow thru the ADC */

		&uart1 {
		status = "okay";
		};

		&uart2 {
		status = "okay";
		};

		&uart3 {
		status = "okay";
		};

arch/arm/boot/dts/rk3066a-clocks.dtsi

deleted100644 → 0

+0 −299

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013 MundoReader S.L.
		* Author: Heiko Stuebner <heiko@sntech.de>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		/ {
		clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		* This is a dummy clock, to be used as placeholder on
		* other mux clocks when a specific parent clock is not
		* yet implemented. It should be dropped when the driver
		* is complete.
		*/
		dummy: dummy {
		compatible = "fixed-clock";
		clock-frequency = <0>;
		#clock-cells = <0>;
		};

		xin24m: xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
		};

		dummy48m: dummy48m {
		compatible = "fixed-clock";
		clock-frequency = <48000000>;
		#clock-cells = <0>;
		};

		dummy150m: dummy150m {
		compatible = "fixed-clock";
		clock-frequency = <150000000>;
		#clock-cells = <0>;
		};

		clk_gates0: gate-clk@200000d0 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000d0 0x4>;
		clocks = <&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>;

		clock-output-names =
		"gate_core_periph", "gate_cpu_gpll",
		"gate_ddrphy", "gate_aclk_cpu",
		"gate_hclk_cpu", "gate_pclk_cpu",
		"gate_atclk_cpu", "gate_i2s0",
		"gate_i2s0_frac", "gate_i2s1",
		"gate_i2s1_frac", "gate_i2s2",
		"gate_i2s2_frac", "gate_spdif",
		"gate_spdif_frac", "gate_testclk";

		#clock-cells = <1>;
		};

		clk_gates1: gate-clk@200000d4 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000d4 0x4>;
		clocks = <&xin24m>, <&xin24m>,
		<&xin24m>, <&dummy>,
		<&dummy>, <&xin24m>,
		<&xin24m>, <&dummy>,
		<&xin24m>, <&dummy>,
		<&xin24m>, <&dummy>,
		<&xin24m>, <&dummy>,
		<&xin24m>, <&dummy>;

		clock-output-names =
		"gate_timer0", "gate_timer1",
		"gate_timer2", "gate_jtag",
		"gate_aclk_lcdc1_src", "gate_otgphy0",
		"gate_otgphy1", "gate_ddr_gpll",
		"gate_uart0", "gate_frac_uart0",
		"gate_uart1", "gate_frac_uart1",
		"gate_uart2", "gate_frac_uart2",
		"gate_uart3", "gate_frac_uart3";

		#clock-cells = <1>;
		};

		clk_gates2: gate-clk@200000d8 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000d8 0x4>;
		clocks = <&clk_gates2 1>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&clk_gates2 3>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy48m>,
		<&dummy>, <&dummy48m>,
		<&dummy>, <&dummy>;

		clock-output-names =
		"gate_periph_src", "gate_aclk_periph",
		"gate_hclk_periph", "gate_pclk_periph",
		"gate_smc", "gate_mac",
		"gate_hsadc", "gate_hsadc_frac",
		"gate_saradc", "gate_spi0",
		"gate_spi1", "gate_mmc0",
		"gate_mac_lbtest", "gate_mmc1",
		"gate_emmc", "gate_tsadc";

		#clock-cells = <1>;
		};

		clk_gates3: gate-clk@200000dc {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000dc 0x4>;
		clocks = <&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>, <&dummy>;

		clock-output-names =
		"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
		"gate_dclk_lcdc1", "gate_pclkin_cif0",
		"gate_pclkin_cif1", "reserved",
		"reserved", "gate_cif0_out",
		"gate_cif1_out", "gate_aclk_vepu",
		"gate_hclk_vepu", "gate_aclk_vdpu",
		"gate_hclk_vdpu", "gate_gpu_src",
		"reserved", "gate_xin27m";

		#clock-cells = <1>;
		};

		clk_gates4: gate-clk@200000e0 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000e0 0x4>;
		clocks = <&clk_gates2 2>, <&clk_gates2 3>,
		<&clk_gates2 1>, <&clk_gates2 1>,
		<&clk_gates2 1>, <&clk_gates2 2>,
		<&clk_gates2 2>, <&clk_gates2 2>,
		<&clk_gates0 4>, <&clk_gates0 4>,
		<&clk_gates0 3>, <&clk_gates0 3>,
		<&clk_gates0 3>, <&clk_gates2 3>,
		<&clk_gates0 4>;

		clock-output-names =
		"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
		"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
		"gate_aclk_pei_niu", "gate_hclk_usb_peri",
		"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
		"gate_hclk_cpubus", "gate_hclk_ahb2apb",
		"gate_aclk_strc_sys", "gate_aclk_l2mem_con",
		"gate_aclk_intmem", "gate_pclk_tsadc",
		"gate_hclk_hdmi";

		#clock-cells = <1>;
		};

		clk_gates5: gate-clk@200000e4 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000e4 0x4>;
		clocks = <&clk_gates0 3>, <&clk_gates2 1>,
		<&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates0 4>, <&clk_gates0 5>,
		<&clk_gates2 1>, <&clk_gates2 2>,
		<&clk_gates2 2>, <&clk_gates2 2>,
		<&clk_gates2 2>, <&clk_gates4 5>,
		<&clk_gates4 5>, <&dummy>;

		clock-output-names =
		"gate_aclk_dmac1", "gate_aclk_dmac2",
		"gate_pclk_efuse", "gate_pclk_tzpc",
		"gate_pclk_grf", "gate_pclk_pmu",
		"gate_hclk_rom", "gate_pclk_ddrupctl",
		"gate_aclk_smc", "gate_hclk_nandc",
		"gate_hclk_mmc0", "gate_hclk_mmc1",
		"gate_hclk_emmc", "gate_hclk_otg0",
		"gate_hclk_otg1", "gate_aclk_gpu";

		#clock-cells = <1>;
		};

		clk_gates6: gate-clk@200000e8 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000e8 0x4>;
		clocks = <&clk_gates3 0>, <&clk_gates0 4>,
		<&clk_gates0 4>, <&clk_gates1 4>,
		<&clk_gates0 4>, <&clk_gates3 0>,
		<&clk_gates0 4>, <&clk_gates1 4>,
		<&clk_gates3 0>, <&clk_gates0 4>,
		<&clk_gates0 4>, <&clk_gates1 4>,
		<&clk_gates0 4>, <&clk_gates3 0>,
		<&dummy>, <&dummy>;

		clock-output-names =
		"gate_aclk_lcdc0", "gate_hclk_lcdc0",
		"gate_hclk_lcdc1", "gate_aclk_lcdc1",
		"gate_hclk_cif0", "gate_aclk_cif0",
		"gate_hclk_cif1", "gate_aclk_cif1",
		"gate_aclk_ipp", "gate_hclk_ipp",
		"gate_hclk_rga", "gate_aclk_rga",
		"gate_hclk_vio_bus", "gate_aclk_vio0",
		"gate_aclk_vcodec", "gate_shclk_vio_h2h";

		#clock-cells = <1>;
		};

		clk_gates7: gate-clk@200000ec {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000ec 0x4>;
		clocks = <&clk_gates2 2>, <&clk_gates0 4>,
		<&clk_gates0 4>, <&clk_gates0 4>,
		<&clk_gates0 4>, <&clk_gates2 2>,
		<&clk_gates2 2>, <&clk_gates0 5>,
		<&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates0 5>, <&clk_gates2 3>,
		<&clk_gates2 3>, <&clk_gates2 3>,
		<&clk_gates2 3>, <&clk_gates2 3>;

		clock-output-names =
		"gate_hclk_emac", "gate_hclk_spdif",
		"gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
		"gate_hclk_i2s_8ch", "gate_hclk_hsadc",
		"gate_hclk_pidf", "gate_pclk_timer0",
		"gate_pclk_timer1", "gate_pclk_timer2",
		"gate_pclk_pwm01", "gate_pclk_pwm23",
		"gate_pclk_spi0", "gate_pclk_spi1",
		"gate_pclk_saradc", "gate_pclk_wdt";

		#clock-cells = <1>;
		};

		clk_gates8: gate-clk@200000f0 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000f0 0x4>;
		clocks = <&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates2 3>, <&clk_gates2 3>,
		<&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates2 3>, <&clk_gates2 3>,
		<&clk_gates2 3>, <&clk_gates0 5>,
		<&clk_gates0 5>, <&clk_gates0 5>,
		<&clk_gates2 3>, <&clk_gates2 3>,
		<&dummy>, <&clk_gates0 5>;

		clock-output-names =
		"gate_pclk_uart0", "gate_pclk_uart1",
		"gate_pclk_uart2", "gate_pclk_uart3",
		"gate_pclk_i2c0", "gate_pclk_i2c1",
		"gate_pclk_i2c2", "gate_pclk_i2c3",
		"gate_pclk_i2c4", "gate_pclk_gpio0",
		"gate_pclk_gpio1", "gate_pclk_gpio2",
		"gate_pclk_gpio3", "gate_pclk_gpio4",
		"reserved", "gate_pclk_gpio6";

		#clock-cells = <1>;
		};

		clk_gates9: gate-clk@200000f4 {
		compatible = "rockchip,rk2928-gate-clk";
		reg = <0x200000f4 0x4>;
		clocks = <&dummy>, <&clk_gates0 5>,
		<&dummy>, <&dummy>,
		<&dummy>, <&clk_gates1 4>,
		<&clk_gates0 5>, <&dummy>,
		<&dummy>, <&dummy>,
		<&dummy>;

		clock-output-names =
		"gate_clk_core_dbg", "gate_pclk_dbg",
		"gate_clk_trace", "gate_atclk",
		"gate_clk_l2c", "gate_aclk_vio1",
		"gate_pclk_publ", "gate_aclk_intmem0",
		"gate_aclk_intmem1", "gate_aclk_intmem2",
		"gate_aclk_intmem3";

		#clock-cells = <1>;
		};
		};

		};

arch/arm/boot/dts/rk3066a.dtsi

+328 −187

Original line number	Diff line number	Diff line
		@@ -15,8 +15,8 @@

		#include <dt-bindings/gpio/gpio.h>
		#include <dt-bindings/pinctrl/rockchip.h>
		#include <dt-bindings/clock/rk3066a-cru.h>
		#include "rk3xxx.dtsi"
		#include "rk3066a-clocks.dtsi"

		/ {
		compatible = "rockchip,rk3066a";
		@@ -40,45 +40,53 @@
		};
		};

		soc {
		timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates1 0>, <&clk_gates7 7>;
		clock-names = "timer", "pclk";
		sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
		compatible = "rockchip,rk3066-smp-sram";
		reg = <0x0 0x50>;
		};
		};

		timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates1 1>, <&clk_gates7 8>;
		clock-names = "timer", "pclk";
		cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates1 2>, <&clk_gates7 9>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
		};

		sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
		compatible = "rockchip,rk3066-smp-sram";
		reg = <0x0 0x50>;
		timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
		};

		timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
		};

		pinctrl@20008000 {
		pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		@@ -89,7 +97,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x20034000 0x100>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 9>;
		clocks = <&cru PCLK_GPIO0>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -102,7 +110,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x2003c000 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 10>;
		clocks = <&cru PCLK_GPIO1>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -115,7 +123,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x2003e000 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 11>;
		clocks = <&cru PCLK_GPIO2>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -128,7 +136,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x20080000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 12>;
		clocks = <&cru PCLK_GPIO3>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -141,7 +149,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x20084000 0x100>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 13>;
		clocks = <&cru PCLK_GPIO4>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -154,7 +162,7 @@
		compatible = "rockchip,gpio-bank";
		reg = <0x2000a000 0x100>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates8 15>;
		clocks = <&cru PCLK_GPIO6>;

		gpio-controller;
		#gpio-cells = <2>;
		@@ -171,6 +179,65 @@
		bias-disable;
		};

		i2c0 {
		i2c0_xfer: i2c0-xfer {
		rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
		<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		i2c1 {
		i2c1_xfer: i2c1-xfer {
		rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
		<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		i2c2 {
		i2c2_xfer: i2c2-xfer {
		rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
		<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		i2c3 {
		i2c3_xfer: i2c3-xfer {
		rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
		<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
		};
		};

		i2c4 {
		i2c4_xfer: i2c4-xfer {
		rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
		<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		pwm0 {
		pwm0_out: pwm0-out {
		rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		pwm1 {
		pwm1_out: pwm1-out {
		rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		pwm2 {
		pwm2_out: pwm2-out {
		rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		pwm3 {
		pwm3_out: pwm3-out {
		rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
		};
		};

		uart0 {
		uart0_xfer: uart0-xfer {
		rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
		@@ -283,4 +350,78 @@
		};
		};
		};

		&i2c0 {
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		};

		&i2c1 {
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		};

		&i2c2 {
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		};

		&i2c3 {
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		};

		&i2c4 {
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_xfer>;
		};

		&mmc0 {
		pinctrl-names = "default";
		pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
		};

		&mmc1 {
		pinctrl-names = "default";
		pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
		};

		&pwm0 {
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_out>;
		};

		&pwm1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_out>;
		};

		&pwm2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_out>;
		};

		&pwm3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3_out>;
		};

		&uart0 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer>;
		};

		&uart1 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		};

		&uart2 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		};

		&uart3 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart3_xfer>;
		};

arch/arm/boot/dts/rk3188-clocks.dtsi

deleted100644 → 0

+0 −289

File deleted.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/rk3188-radxarock.dts

+180 −36

Original line number	Diff line number	Diff line
		@@ -23,25 +23,6 @@
		reg = <0x60000000 0x80000000>;
		};

		soc {
		uart0: serial@10124000 {
		status = "okay";
		};

		uart1: serial@10126000 {
		status = "okay";
		};

		uart2: serial@20064000 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "okay";
		};

		uart3: serial@20068000 {
		status = "okay";
		};

		gpio-keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		@@ -77,5 +58,168 @@
		};
		};

		ir_recv: gpio-ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio0 10 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&ir_recv_pin>;
		};

		vcc_sd0: sdmmc-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sdmmc-supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
		};
		};

		&i2c1 {
		status = "okay";
		clock-frequency = <400000>;

		act8846: act8846@5a {
		compatible = "active-semi,act8846";
		reg = <0x5a>;
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&act8846_dvs0_ctl>;

		regulators {
		vcc_ddr: REG1 {
		regulator-name = "VCC_DDR";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		};

		vdd_log: REG2 {
		regulator-name = "VDD_LOG";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-always-on;
		};

		vdd_arm: REG3 {
		regulator-name = "VDD_ARM";
		regulator-min-microvolt = <875000>;
		regulator-max-microvolt = <1300000>;
		regulator-always-on;
		};

		vcc_io: REG4 {
		regulator-name = "VCC_IO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		};

		vdd_10: REG5 {
		regulator-name = "VDD_10";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-always-on;
		};

		vdd_hdmi: REG6 {
		regulator-name = "VDD_HDMI";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
		};

		vcc18: REG7 {
		regulator-name = "VCC_18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		};

		vcca_33: REG8 {
		regulator-name = "VCCA_33";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		};

		vcc_rmii: REG9 {
		regulator-name = "VCC_RMII";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		};

		vccio_wl: REG10 {
		regulator-name = "VCCIO_WL";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		};

		vcc_18: REG11 {
		regulator-name = "VCC18_IO";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		};

		vcc28: REG12 {
		regulator-name = "VCC_28";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		regulator-always-on;
		};
		};
		};
		};

		&mmc0 {
		num-slots = <1>;
		status = "okay";
		vmmc-supply = <&vcc_sd0>;

		slot@0 {
		reg = <0>;
		bus-width = <4>;
		disable-wp;
		};
		};

		&pinctrl {
		pcfg_output_low: pcfg-output-low {
		output-low;
		};

		act8846 {
		act8846_dvs0_ctl: act8846-dvs0-ctl {
		rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
		};
		};

		ir-receiver {
		ir_recv_pin: ir-recv-pin {
		rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
		};
		};
		};

		&uart0 {
		status = "okay";
		};

		&uart1 {
		status = "okay";
		};

		&uart2 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "okay";
		};

		&uart3 {
		status = "okay";
		};