i2c: qcom: geni: Modify FIFO mode sequencing and error handling

Initializing registers like IRQ_CLEAR more than once can lead to
part of the interrupt status being cleared leading to timeout.
Avoid initializing registers more than once when transfer mode is
FIFO, and modify relevant error reporting of RX and TX FIFO status
registers to make sure DMA registers aren't printed if FIFO mode
transactions report an error.

Change-Id: Ibde688d99286f336eda99271fb4fc879cff30ddc
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>