Loading drivers/gpu/msm/adreno_a6xx.c +21 −22 Original line number Diff line number Diff line Loading @@ -364,7 +364,7 @@ static struct reg_list_pair a6xx_ifpc_pwrup_reglist[] = { { A6XX_CP_AHB_CNTL, 0x0 }, }; static struct reg_list_pair a615_ifpc_pwrup_reglist[] = { static struct reg_list_pair a615_pwrup_reglist[] = { { A6XX_UCHE_GBIF_GX_CONFIG, 0x0 }, }; Loading Loading @@ -604,7 +604,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) uint32_t i; struct cpu_gpu_lock *lock; struct reg_list_pair *r; uint16_t a615_list_size = 0; /* Set up the register values */ for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_pwrup_reglist); i++) { Loading @@ -617,19 +616,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } if (adreno_is_a615(adreno_dev)) { for (i = 0; i < ARRAY_SIZE(a615_ifpc_pwrup_reglist); i++) { r = &a615_ifpc_pwrup_reglist[i]; kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } a615_list_size = sizeof(a615_ifpc_pwrup_reglist); memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock), a615_ifpc_pwrup_reglist, a615_list_size); } lock = (struct cpu_gpu_lock *) adreno_dev->pwrup_reglist.hostptr; lock->flag_ucode = 0; lock->flag_kmd = 0; Loading @@ -648,16 +634,29 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) * of the static IFPC-only register list. */ lock->list_length = (sizeof(a6xx_ifpc_pwrup_reglist) + sizeof(a6xx_pwrup_reglist) + a615_list_size) >> 2; lock->list_offset = (sizeof(a6xx_ifpc_pwrup_reglist) + a615_list_size) >> 2; sizeof(a6xx_pwrup_reglist)) >> 2; lock->list_offset = sizeof(a6xx_ifpc_pwrup_reglist) >> 2; memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + a615_list_size, memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock), a6xx_ifpc_pwrup_reglist, sizeof(a6xx_ifpc_pwrup_reglist)); memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + sizeof(a6xx_ifpc_pwrup_reglist) + a615_list_size, a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist)); + sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist)); if (adreno_is_a615(adreno_dev)) { for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) { r = &a615_pwrup_reglist[i]; kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + sizeof(a6xx_ifpc_pwrup_reglist) + sizeof(a6xx_pwrup_reglist), a615_pwrup_reglist, sizeof(a615_pwrup_reglist)); lock->list_length += sizeof(a615_pwrup_reglist); } } /* Loading Loading
drivers/gpu/msm/adreno_a6xx.c +21 −22 Original line number Diff line number Diff line Loading @@ -364,7 +364,7 @@ static struct reg_list_pair a6xx_ifpc_pwrup_reglist[] = { { A6XX_CP_AHB_CNTL, 0x0 }, }; static struct reg_list_pair a615_ifpc_pwrup_reglist[] = { static struct reg_list_pair a615_pwrup_reglist[] = { { A6XX_UCHE_GBIF_GX_CONFIG, 0x0 }, }; Loading Loading @@ -604,7 +604,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) uint32_t i; struct cpu_gpu_lock *lock; struct reg_list_pair *r; uint16_t a615_list_size = 0; /* Set up the register values */ for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_pwrup_reglist); i++) { Loading @@ -617,19 +616,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } if (adreno_is_a615(adreno_dev)) { for (i = 0; i < ARRAY_SIZE(a615_ifpc_pwrup_reglist); i++) { r = &a615_ifpc_pwrup_reglist[i]; kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } a615_list_size = sizeof(a615_ifpc_pwrup_reglist); memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock), a615_ifpc_pwrup_reglist, a615_list_size); } lock = (struct cpu_gpu_lock *) adreno_dev->pwrup_reglist.hostptr; lock->flag_ucode = 0; lock->flag_kmd = 0; Loading @@ -648,16 +634,29 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) * of the static IFPC-only register list. */ lock->list_length = (sizeof(a6xx_ifpc_pwrup_reglist) + sizeof(a6xx_pwrup_reglist) + a615_list_size) >> 2; lock->list_offset = (sizeof(a6xx_ifpc_pwrup_reglist) + a615_list_size) >> 2; sizeof(a6xx_pwrup_reglist)) >> 2; lock->list_offset = sizeof(a6xx_ifpc_pwrup_reglist) >> 2; memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + a615_list_size, memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock), a6xx_ifpc_pwrup_reglist, sizeof(a6xx_ifpc_pwrup_reglist)); memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + sizeof(a6xx_ifpc_pwrup_reglist) + a615_list_size, a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist)); + sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist)); if (adreno_is_a615(adreno_dev)) { for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) { r = &a615_pwrup_reglist[i]; kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); } memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) + sizeof(a6xx_ifpc_pwrup_reglist) + sizeof(a6xx_pwrup_reglist), a615_pwrup_reglist, sizeof(a615_pwrup_reglist)); lock->list_length += sizeof(a615_pwrup_reglist); } } /* Loading