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Commit 35dde697 authored by Akhil P Oommen's avatar Akhil P Oommen
Browse files

msm: kgsl: Update powerup register list for A615 GPU 



GPU_UCHE_GBIF_GX_CONFIG is programmed as a part of a hardware quirk to
limit the number of read/write transactions from UCHE block to GBIF.
Move this from IFPC powerup register list to IFPC + Preemption register
list to make sure it's value is restored during preemption context switch.

Change-Id: I967ff0cdbbee2599c9fc08d13de7a3345b65aee3
Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
parent c95d89c3

drivers/gpu/msm/adreno_a6xx.c

+21 −22
Original line number Diff line number Diff line
@@ -364,7 +364,7 @@ static struct reg_list_pair a6xx_ifpc_pwrup_reglist[] = { 
	{ A6XX_CP_AHB_CNTL, 0x0 },

};



static struct reg_list_pair a615_ifpc_pwrup_reglist[] = {

static struct reg_list_pair a615_pwrup_reglist[] = {

	{ A6XX_UCHE_GBIF_GX_CONFIG, 0x0 },

};
@@ -604,7 +604,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
	uint32_t i;

	struct cpu_gpu_lock *lock;

	struct reg_list_pair *r;

	uint16_t a615_list_size = 0;



	/* Set up the register values */

	for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_pwrup_reglist); i++) {
@@ -617,19 +616,6 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
		kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val);

	}



	if (adreno_is_a615(adreno_dev)) {

		for (i = 0; i < ARRAY_SIZE(a615_ifpc_pwrup_reglist); i++) {

			r = &a615_ifpc_pwrup_reglist[i];

			kgsl_regread(KGSL_DEVICE(adreno_dev),

				r->offset, &r->val);

		}



		a615_list_size = sizeof(a615_ifpc_pwrup_reglist);



		memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock),

			a615_ifpc_pwrup_reglist, a615_list_size);

	}



	lock = (struct cpu_gpu_lock *) adreno_dev->pwrup_reglist.hostptr;

	lock->flag_ucode = 0;

	lock->flag_kmd = 0;
@@ -648,16 +634,29 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
	 * of the static IFPC-only register list.

	 */

	lock->list_length = (sizeof(a6xx_ifpc_pwrup_reglist) +

			sizeof(a6xx_pwrup_reglist) + a615_list_size) >> 2;

	lock->list_offset = (sizeof(a6xx_ifpc_pwrup_reglist) +

			a615_list_size) >> 2;

			sizeof(a6xx_pwrup_reglist)) >> 2;

	lock->list_offset = sizeof(a6xx_ifpc_pwrup_reglist) >> 2;



	memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)

		+ a615_list_size,

	memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock),

		a6xx_ifpc_pwrup_reglist, sizeof(a6xx_ifpc_pwrup_reglist));

	memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)

		+ sizeof(a6xx_ifpc_pwrup_reglist) + a615_list_size,

		a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist));

		+ sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist,

		sizeof(a6xx_pwrup_reglist));



	if (adreno_is_a615(adreno_dev)) {

		for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) {

			r = &a615_pwrup_reglist[i];

			kgsl_regread(KGSL_DEVICE(adreno_dev),

				r->offset, &r->val);

		}



		memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)

			+ sizeof(a6xx_ifpc_pwrup_reglist)

			+ sizeof(a6xx_pwrup_reglist), a615_pwrup_reglist,

			sizeof(a615_pwrup_reglist));



		lock->list_length += sizeof(a615_pwrup_reglist);

	}

}



/*