Loading drivers/gpu/drm/msm/sde/sde_encoder_phys.h +4 −2 Original line number Diff line number Diff line Loading @@ -285,13 +285,15 @@ static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys) * @base: Baseclass physical encoder structure * @hw_intf: Hardware interface to the intf registers * @timing_params: Current timing parameter * @rot_prefill_line: number of line to prefill for inline rotation; 0 disable * @rot_fetch: Prefill for inline rotation * @rot_fetch_valid: true if rot_fetch is updated (reset in enc enable) */ struct sde_encoder_phys_vid { struct sde_encoder_phys base; struct sde_hw_intf *hw_intf; struct intf_timing_params timing_params; u64 rot_prefill_line; struct intf_prog_fetch rot_fetch; bool rot_fetch_valid; }; /** Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +11 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,11 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, } } /* return if rot_fetch does not change since last update */ if (vid_enc->rot_fetch_valid && !memcmp(&vid_enc->rot_fetch, &f, sizeof(f))) return; SDE_DEBUG_VIDENC(vid_enc, "rot_fetch_lines %u rot_fetch_start_vsync_counter %u\n", rot_fetch_lines, rot_fetch_start_vsync_counter); Loading @@ -294,6 +299,9 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); vid_enc->hw_intf->ops.setup_rot_start(vid_enc->hw_intf, &f); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); vid_enc->rot_fetch = f; vid_enc->rot_fetch_valid = true; } static bool sde_encoder_phys_vid_mode_fixup( Loading Loading @@ -587,6 +595,9 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing)) return; /* reset state variables until after first update */ vid_enc->rot_fetch_valid = false; sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx); sde_encoder_phys_vid_setup_timing_engine(phys_enc); Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys.h +4 −2 Original line number Diff line number Diff line Loading @@ -285,13 +285,15 @@ static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys) * @base: Baseclass physical encoder structure * @hw_intf: Hardware interface to the intf registers * @timing_params: Current timing parameter * @rot_prefill_line: number of line to prefill for inline rotation; 0 disable * @rot_fetch: Prefill for inline rotation * @rot_fetch_valid: true if rot_fetch is updated (reset in enc enable) */ struct sde_encoder_phys_vid { struct sde_encoder_phys base; struct sde_hw_intf *hw_intf; struct intf_timing_params timing_params; u64 rot_prefill_line; struct intf_prog_fetch rot_fetch; bool rot_fetch_valid; }; /** Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +11 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,11 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, } } /* return if rot_fetch does not change since last update */ if (vid_enc->rot_fetch_valid && !memcmp(&vid_enc->rot_fetch, &f, sizeof(f))) return; SDE_DEBUG_VIDENC(vid_enc, "rot_fetch_lines %u rot_fetch_start_vsync_counter %u\n", rot_fetch_lines, rot_fetch_start_vsync_counter); Loading @@ -294,6 +299,9 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); vid_enc->hw_intf->ops.setup_rot_start(vid_enc->hw_intf, &f); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); vid_enc->rot_fetch = f; vid_enc->rot_fetch_valid = true; } static bool sde_encoder_phys_vid_mode_fixup( Loading Loading @@ -587,6 +595,9 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing)) return; /* reset state variables until after first update */ vid_enc->rot_fetch_valid = false; sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx); sde_encoder_phys_vid_setup_timing_engine(phys_enc); Loading