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Commit 15fde110 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86: Only dump PEBS register when PEBS has been detected 



Technically PEBS_ENABLED is only guaranteed to exist when we
detected PEBS. So add a check for this to the PMU dump function.
I don't think it can happen on a real CPU, but could in a VM.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1425059312-18217-4-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent da3e606d

arch/x86/kernel/cpu/perf_event.c

+4 −2
Original line number Diff line number Diff line
@@ -1189,14 +1189,16 @@ void perf_event_print_debug(void) 
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);

		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);

		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);

		rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);



		pr_info("\n");

		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);

		pr_info("CPU#%d: status:     %016llx\n", cpu, status);

		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);

		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);

		if (x86_pmu.pebs_constraints) {

			rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);

			pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);

		}

		if (x86_pmu.lbr_nr) {

			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);

			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);