Loading Makefile +4 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 38 SUBLEVEL = 40 EXTRAVERSION = NAME = Roaring Lionus Loading Loading @@ -633,6 +633,9 @@ include arch/$(SRCARCH)/Makefile KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) KBUILD_CFLAGS += $(call cc-disable-warning,frame-address,) KBUILD_CFLAGS += $(call cc-disable-warning, format-truncation) KBUILD_CFLAGS += $(call cc-disable-warning, format-overflow) KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context) ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) Loading arch/arm/include/asm/elf.h +2 −6 Original line number Diff line number Diff line Loading @@ -112,12 +112,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) /* This is the base location for PIE (ET_DYN with INTERP) loads. */ #define ELF_ET_DYN_BASE 0x400000UL /* When the program starts, a1 contains a pointer to a function to be registered with atexit, as per the SVR4 ABI. A value of 0 means we Loading arch/arm64/boot/dts/marvell/armada-37xx.dtsi +4 −8 Original line number Diff line number Diff line Loading @@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc { Loading arch/arm64/include/asm/elf.h +6 −6 Original line number Diff line number Diff line Loading @@ -113,12 +113,11 @@ #define ELF_EXEC_PAGESIZE PAGE_SIZE /* * This is the location that an ET_DYN program is loaded if exec'ed. Typical * use of this is to invoke "./ld.so someprog" to test out a new version of * the loader. We need to make sure that it is out of the way of the program * that it will "exec", and that there is sufficient room for the brk. * This is the base location for PIE (ET_DYN with INTERP) loads. On * 64-bit, this is raised to 4GB to leave the entire 32-bit address * space open for things that want to use the area for 32-bit pointers. */ #define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) #define ELF_ET_DYN_BASE 0x100000000UL #ifndef __ASSEMBLY__ Loading Loading @@ -169,7 +168,8 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm, #ifdef CONFIG_COMPAT #define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3) /* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */ #define COMPAT_ELF_ET_DYN_BASE 0x000400000UL /* AArch32 registers. */ #define COMPAT_ELF_NGREG 18 Loading arch/mips/include/asm/branch.h +1 −4 Original line number Diff line number Diff line Loading @@ -74,10 +74,7 @@ static inline int compute_return_epc(struct pt_regs *regs) return __microMIPS_compute_return_epc(regs); if (cpu_has_mips16) return __MIPS16e_compute_return_epc(regs); return regs->cp0_epc; } if (!delay_slot(regs)) { } else if (!delay_slot(regs)) { regs->cp0_epc += 4; return 0; } Loading Loading
Makefile +4 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 38 SUBLEVEL = 40 EXTRAVERSION = NAME = Roaring Lionus Loading Loading @@ -633,6 +633,9 @@ include arch/$(SRCARCH)/Makefile KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) KBUILD_CFLAGS += $(call cc-disable-warning,frame-address,) KBUILD_CFLAGS += $(call cc-disable-warning, format-truncation) KBUILD_CFLAGS += $(call cc-disable-warning, format-overflow) KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context) ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) Loading
arch/arm/include/asm/elf.h +2 −6 Original line number Diff line number Diff line Loading @@ -112,12 +112,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) /* This is the base location for PIE (ET_DYN with INTERP) loads. */ #define ELF_ET_DYN_BASE 0x400000UL /* When the program starts, a1 contains a pointer to a function to be registered with atexit, as per the SVR4 ABI. A value of 0 means we Loading
arch/arm64/boot/dts/marvell/armada-37xx.dtsi +4 −8 Original line number Diff line number Diff line Loading @@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc { Loading
arch/arm64/include/asm/elf.h +6 −6 Original line number Diff line number Diff line Loading @@ -113,12 +113,11 @@ #define ELF_EXEC_PAGESIZE PAGE_SIZE /* * This is the location that an ET_DYN program is loaded if exec'ed. Typical * use of this is to invoke "./ld.so someprog" to test out a new version of * the loader. We need to make sure that it is out of the way of the program * that it will "exec", and that there is sufficient room for the brk. * This is the base location for PIE (ET_DYN with INTERP) loads. On * 64-bit, this is raised to 4GB to leave the entire 32-bit address * space open for things that want to use the area for 32-bit pointers. */ #define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) #define ELF_ET_DYN_BASE 0x100000000UL #ifndef __ASSEMBLY__ Loading Loading @@ -169,7 +168,8 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm, #ifdef CONFIG_COMPAT #define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3) /* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */ #define COMPAT_ELF_ET_DYN_BASE 0x000400000UL /* AArch32 registers. */ #define COMPAT_ELF_NGREG 18 Loading
arch/mips/include/asm/branch.h +1 −4 Original line number Diff line number Diff line Loading @@ -74,10 +74,7 @@ static inline int compute_return_epc(struct pt_regs *regs) return __microMIPS_compute_return_epc(regs); if (cpu_has_mips16) return __MIPS16e_compute_return_epc(regs); return regs->cp0_epc; } if (!delay_slot(regs)) { } else if (!delay_slot(regs)) { regs->cp0_epc += 4; return 0; } Loading