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Commit 12f0e670 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2012-07-06' of... 

Merge tag 'drm-intel-next-2012-07-06' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

Daniel writes:
New pull for -next. Highlights:
- rc6/turbo support for hsw (Eugeni)
- improve corner-case of the reset handling code - gpu reset handling
  should be rock-solid now
- support for fb offset > 4096 pixels on gen4+ (yeah, you need some fairly
  big screens to hit that)
- the "Flush Me Harder" patch to fix the gen6+ fallout from disabling the
  flushing_list
- no more /dev/agpgart on gen6+!
- HAS_PCH_xxx improvements from Paulo
- a few minor bits&pieces all over, most of it in thew hsw code

* tag 'drm-intel-next-2012-07-06' of git://people.freedesktop.org/~danvet/drm-intel: (40 commits)
  drm/i915: program FDI_RX TP and FDI delays
  drm/i915: introduce for_each_encoder_on_crtc
  drm/i915: adjust framebuffer base address on gen4+
  drm/i915: introduce crtc->dspaddr_offset
  drm/i915: Reject page flips with changed format/offset/pitch
  drm/i915: Zero initialize mode_cmd
  drm/i915: don't return a spurious -EIO from intel_ring_begin
  drm/i915: properly SIGBUS on I/O errors
  drm/i915: don't hang userspace when the gpu reset is stuck
  drm/i915: non-interruptible sleeps can't handle -EAGAIN
  drm/i915: don't trylock in the gpu reset code
  drm/i915: fix PIPE_DDI_PORT_MASK
  drm/i915: prevent bogus intel_update_fbc notifications
  drm/i915: re-initialize DDI buffer translations after resume
  drm/i915: don't ironlake_init_pch_refclk() on LPT
  drm/i915: get rid of dev_priv->info->has_pch_split
  drm/i915: add PCH_NONE to enum intel_pch
  drm/i915: prefer wide & slow to fast & narrow in DP configs
  drm/i915: fix up ilk rc6 disabling confusion
  drm/i915: move force wake support into intel_pm
  ...
parents 74da01dc 4acf5186

drivers/char/agp/intel-agp.c

+0 −11
Original line number Diff line number Diff line
@@ -903,17 +903,6 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),

	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),

	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),

	ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),

	ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),

	ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),

	ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),

	ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),

	{ }

};

drivers/gpu/drm/i915/i915_dma.c

+5 −4
Original line number Diff line number Diff line
@@ -1414,7 +1414,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) 
	if (!ap)

		return;



	ap->ranges[0].base = dev_priv->dev->agp->base;

	ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;

	ap->ranges[0].size =

		dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;

	primary =
@@ -1547,7 +1547,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		goto out_mtrrfree;

	}



	/* This must be called before any calls to HAS_PCH_* */

	intel_detect_pch(dev);



	intel_irq_init(dev);

	intel_gt_init(dev);



	/* Try to make sure MCHBAR is enabled before poking at it */

	intel_setup_mchbar(dev);
@@ -1580,7 +1584,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (!IS_I945G(dev) && !IS_I945GM(dev))

		pci_enable_msi(dev->pdev);



	spin_lock_init(&dev_priv->gt_lock);

	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->error_lock);

	spin_lock_init(&dev_priv->rps_lock);
@@ -1599,8 +1602,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	/* Start out suspended */

	dev_priv->mm.suspended = 1;



	intel_detect_pch(dev);



	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		ret = i915_load_modeset_init(dev);

		if (ret < 0) {

drivers/gpu/drm/i915/i915_drv.c

+22 −150
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include "drm.h"

#include "i915_drm.h"

#include "i915_drv.h"

#include "i915_trace.h"

#include "intel_drv.h"



#include <linux/console.h>
@@ -215,7 +216,6 @@ static const struct intel_device_info intel_ironlake_d_info = { 
	.gen = 5,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_bsd_ring = 1,

	.has_pch_split = 1,

};



static const struct intel_device_info intel_ironlake_m_info = {
@@ -223,7 +223,6 @@ static const struct intel_device_info intel_ironlake_m_info = { 
	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_fbc = 1,

	.has_bsd_ring = 1,

	.has_pch_split = 1,

};



static const struct intel_device_info intel_sandybridge_d_info = {
@@ -232,7 +231,6 @@ static const struct intel_device_info intel_sandybridge_d_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -243,7 +241,6 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -253,7 +250,6 @@ static const struct intel_device_info intel_ivybridge_d_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -264,7 +260,6 @@ static const struct intel_device_info intel_ivybridge_m_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -292,7 +287,6 @@ static const struct intel_device_info intel_haswell_d_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -302,7 +296,6 @@ static const struct intel_device_info intel_haswell_m_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};
@@ -432,135 +425,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) 
	return 1;

}



void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))

		udelay(10);



	I915_WRITE_NOTRACE(FORCEWAKE, 1);

	POSTING_READ(FORCEWAKE);



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)

		udelay(10);

}



void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)

{

	int count;



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))

		udelay(10);



	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));

	POSTING_READ(FORCEWAKE_MT);



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)

		udelay(10);

}



/*

 * Generally this is called implicitly by the register read function. However,

 * if some sequence requires the GT to not power down then this function should

 * be called at the beginning of the sequence followed by a call to

 * gen6_gt_force_wake_put() at the end of the sequence.

 */

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	unsigned long irqflags;



	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);

	if (dev_priv->forcewake_count++ == 0)

		dev_priv->display.force_wake_get(dev_priv);

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);

}



static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)

{

	u32 gtfifodbg;

	gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);

	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,

	     "MMIO read or write has been dropped %x\n", gtfifodbg))

		I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);

}



void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE, 0);

	/* The below doubles as a POSTING_READ */

	gen6_gt_check_fifodbg(dev_priv);

}



void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));

	/* The below doubles as a POSTING_READ */

	gen6_gt_check_fifodbg(dev_priv);

}



/*

 * see gen6_gt_force_wake_get()

 */

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	unsigned long irqflags;



	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);

	if (--dev_priv->forcewake_count == 0)

		dev_priv->display.force_wake_put(dev_priv);

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);

}



int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int ret = 0;



	if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {

		int loop = 500;

		u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {

			udelay(10);

			fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

		}

		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))

			++ret;

		dev_priv->gt_fifo_count = fifo;

	}

	dev_priv->gt_fifo_count--;



	return ret;

}



void vlv_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;



	count = 0;



	/* Already awake? */

	if ((I915_READ(0x130094) & 0xa1) == 0xa1)

		return;



	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);

	POSTING_READ(FORCEWAKE_VLV);



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)

		udelay(10);

}



void vlv_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);

	/* FIXME: confirm VLV behavior with Punit folks */

	POSTING_READ(FORCEWAKE_VLV);

}



static int i915_drm_freeze(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -640,7 +504,7 @@ static int i915_drm_thaw(struct drm_device *dev) 


	/* KMS EnterVT equivalent */

	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		if (HAS_PCH_SPLIT(dev))

		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

			ironlake_init_pch_refclk(dev);



		mutex_lock(&dev->struct_mutex);
@@ -797,9 +661,9 @@ static int gen6_do_reset(struct drm_device *dev) 


	/* If reset with a user forcewake, try to restore, otherwise turn it off */

	if (dev_priv->forcewake_count)

		dev_priv->display.force_wake_get(dev_priv);

		dev_priv->gt.force_wake_get(dev_priv);

	else

		dev_priv->display.force_wake_put(dev_priv);

		dev_priv->gt.force_wake_put(dev_priv);



	/* Restore fifo count */

	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
@@ -866,8 +730,7 @@ int i915_reset(struct drm_device *dev) 
	if (!i915_try_reset)

		return 0;



	if (!mutex_trylock(&dev->struct_mutex))

		return -EBUSY;

	mutex_lock(&dev->struct_mutex);



	i915_gem_reset(dev);
@@ -930,10 +793,12 @@ int i915_reset(struct drm_device *dev) 
	return 0;

}





static int __devinit

i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)

{

	struct intel_device_info *intel_info =

		(struct intel_device_info *) ent->driver_data;



	/* Only bind to function 0 of the device. Early generations

	 * used function 1 as a placeholder for multi-head. This causes

	 * us confusion instead, especially on the systems where both
@@ -942,6 +807,18 @@ i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	if (PCI_FUNC(pdev->devfn))

		return -ENODEV;



	/* We've managed to ship a kms-enabled ddx that shipped with an XvMC

	 * implementation for gen3 (and only gen3) that used legacy drm maps

	 * (gasp!) to share buffers between X and the client. Hence we need to

	 * keep around the fake agp stuff for gen3, even when kms is enabled. */

	if (intel_info->gen != 3) {

		driver.driver_features &=

			~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);

	} else if (!intel_agp_enabled) {

		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");

		return -ENODEV;

	}



	return drm_get_pci_dev(pdev, ent, &driver);

}
@@ -1102,11 +979,6 @@ static struct pci_driver i915_pci_driver = { 


static int __init i915_init(void)

{

	if (!intel_agp_enabled) {

		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");

		return -ENODEV;

	}



	driver.num_ioctls = i915_max_ioctl;



	/*
@@ -1239,10 +1111,10 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 
		unsigned long irqflags; \

		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->display.force_wake_get(dev_priv); \

			dev_priv->gt.force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->display.force_wake_put(dev_priv); \

			dev_priv->gt.force_wake_put(dev_priv); \

		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

	} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \

		val = read##y(dev_priv->regs + reg + 0x180000);		\

drivers/gpu/drm/i915/i915_drv.h

+16 −12
Original line number Diff line number Diff line
@@ -79,6 +79,10 @@ enum port { 


#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)



#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \

	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \

		if ((intel_encoder)->base.crtc == (__crtc))



struct intel_pch_pll {

	int refcount; /* count of number of CRTCs sharing this PLL */

	int active; /* count of number of active CRTCs (i.e. DPMS on) */
@@ -262,8 +266,6 @@ struct drm_i915_display_funcs { 
			  struct drm_i915_gem_object *obj);

	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,

			    int x, int y);

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

	/* clock updates for mode set */

	/* cursor updates */

	/* render clock increase/decrease */
@@ -271,6 +273,11 @@ struct drm_i915_display_funcs { 
	/* pll clock increase/decrease */

};



struct drm_i915_gt_funcs {

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

};



struct intel_device_info {

	u8 gen;

	u8 is_mobile:1;
@@ -285,7 +292,6 @@ struct intel_device_info { 
	u8 is_crestline:1;

	u8 is_ivybridge:1;

	u8 is_valleyview:1;

	u8 has_pch_split:1;

	u8 has_force_wake:1;

	u8 is_haswell:1;

	u8 has_fbc:1;
@@ -333,6 +339,7 @@ enum no_fbc_reason { 
};



enum intel_pch {

	PCH_NONE = 0,	/* No PCH present */

	PCH_IBX,	/* Ibexpeak PCH */

	PCH_CPT,	/* Cougarpoint PCH */

	PCH_LPT,	/* Lynxpoint PCH */
@@ -362,6 +369,8 @@ typedef struct drm_i915_private { 
	int relative_constants_mode;



	void __iomem *regs;



	struct drm_i915_gt_funcs gt;

	/** gt_fifo_count and the subsequent register write are synchronized

	 * with dev->struct_mutex. */

	unsigned gt_fifo_count;
@@ -1115,13 +1124,13 @@ struct drm_i915_file_private { 
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)

#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)



#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)

#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)



#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)

#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)

#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)

#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)



#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
@@ -1200,6 +1209,7 @@ void i915_hangcheck_elapsed(unsigned long data); 
void i915_handle_error(struct drm_device *dev, bool wedged);



extern void intel_irq_init(struct drm_device *dev);

extern void intel_gt_init(struct drm_device *dev);



void i915_error_state_free(struct kref *error_ref);
@@ -1330,6 +1340,8 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 


void i915_gem_retire_requests(struct drm_device *dev);

void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);

int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,

				      bool interruptible);



void i915_gem_reset(struct drm_device *dev);

void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
@@ -1510,20 +1522,12 @@ extern bool intel_fbc_enabled(struct drm_device *dev); 
extern void intel_disable_fbc(struct drm_device *dev);

extern bool ironlake_set_drps(struct drm_device *dev, u8 val);

extern void ironlake_init_pch_refclk(struct drm_device *dev);

extern void ironlake_enable_rc6(struct drm_device *dev);

extern void gen6_set_rps(struct drm_device *dev, u8 val);

extern void intel_detect_pch(struct drm_device *dev);

extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);

extern int intel_enable_rc6(const struct drm_device *dev);



extern bool i915_semaphore_is_enabled(struct drm_device *dev);

extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);

extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);



extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);

extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);



/* overlay */

#ifdef CONFIG_DEBUG_FS

drivers/gpu/drm/i915/i915_gem.c

+34 −10
Original line number Diff line number Diff line
@@ -96,9 +96,18 @@ i915_gem_wait_for_error(struct drm_device *dev) 
	if (!atomic_read(&dev_priv->mm.wedged))

		return 0;



	ret = wait_for_completion_interruptible(x);

	if (ret)

	/*

	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging

	 * userspace. If it takes that long something really bad is going on and

	 * we should simply try to bail out and fail as gracefully as possible.

	 */

	ret = wait_for_completion_interruptible_timeout(x, 10*HZ);

	if (ret == 0) {

		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");

		return -EIO;

	} else if (ret < 0) {

		return ret;

	}



	if (atomic_read(&dev_priv->mm.wedged)) {

		/* GPU is hung, bump the completion count to account for
@@ -1132,6 +1141,11 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 
out:

	switch (ret) {

	case -EIO:

		/* If this -EIO is due to a gpu hang, give the reset code a

		 * chance to clean up the mess. Otherwise return the proper

		 * SIGBUS. */

		if (!atomic_read(&dev_priv->mm.wedged))

			return VM_FAULT_SIGBUS;

	case -EAGAIN:

		/* Give the error handler a chance to run and move the

		 * objects off the GPU active list. Next time we service the
@@ -1863,11 +1877,10 @@ i915_gem_retire_work_handler(struct work_struct *work) 
	mutex_unlock(&dev->struct_mutex);

}



static int

i915_gem_check_wedge(struct drm_i915_private *dev_priv)

int

i915_gem_check_wedge(struct drm_i915_private *dev_priv,

		     bool interruptible)

{

	BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));



	if (atomic_read(&dev_priv->mm.wedged)) {

		struct completion *x = &dev_priv->error_completion;

		bool recovery_complete;
@@ -1878,7 +1891,16 @@ i915_gem_check_wedge(struct drm_i915_private *dev_priv) 
		recovery_complete = x->done > 0;

		spin_unlock_irqrestore(&x->wait.lock, flags);



		return recovery_complete ? -EIO : -EAGAIN;

		/* Non-interruptible callers can't handle -EAGAIN, hence return

		 * -EIO unconditionally for these. */

		if (!interruptible)

			return -EIO;



		/* Recovery complete, but still wedged means reset failure. */

		if (recovery_complete)

			return -EIO;



		return -EAGAIN;

	}



	return 0;
@@ -1932,6 +1954,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
	unsigned long timeout_jiffies;

	long end;

	bool wait_forever = true;

	int ret;



	if (i915_seqno_passed(ring->get_seqno(ring), seqno))

		return 0;
@@ -1963,8 +1986,9 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
			end = wait_event_timeout(ring->irq_queue, EXIT_COND,

						 timeout_jiffies);



		if (atomic_read(&dev_priv->mm.wedged))

			end = -EAGAIN;

		ret = i915_gem_check_wedge(dev_priv, interruptible);

		if (ret)

			end = ret;

	} while (end == 0 && wait_forever);



	getrawmonotonic(&now);
@@ -2004,7 +2028,7 @@ i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) 


	BUG_ON(seqno == 0);



	ret = i915_gem_check_wedge(dev_priv);

	ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);

	if (ret)

		return ret;