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Commit 4acf5186 authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Daniel Vetter
Browse files

drm/i915: program FDI_RX TP and FDI delays 



This is required for a stable FDI connection.

v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni.

CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6c2b7c12

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3854,6 +3854,9 @@ 
#define _FDI_RXA_TUSIZE2         0xf0038

#define _FDI_RXB_TUSIZE1         0xf1030

#define _FDI_RXB_TUSIZE2         0xf1038

#define  FDI_RX_TP1_TO_TP2_48	(2<<20)

#define  FDI_RX_TP1_TO_TP2_64	(3<<20)

#define  FDI_RX_FDI_DELAY_90	(0x90<<0)

#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)

#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)

#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)

drivers/gpu/drm/i915/intel_ddi.c

+9 −0
Original line number Diff line number Diff line
@@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 


		udelay(600);



		/* We need to program FDI_RX_MISC with the default TP1 to TP2

		 * values before enabling the receiver, and configure the delay

		 * for the FDI timing generator to 90h. Luckily, all the other

		 * bits are supposed to be zeroed, so we can write those values

		 * directly.

		 */

		I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |

				FDI_RX_FDI_DELAY_90);



		/* Enable CPU FDI Receiver with auto-training */

		reg = FDI_RX_CTL(pipe);

		I915_WRITE(reg,