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Commit 11782b02 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: consolidate swizzling control bit frobbing 



On gen5 we also need to correctly set up swizzling in the display
scanout engine, but only there. Consolidate this into the same
function.

This has a small effect on ums setups - the kernel now also sets this
bit in addition to userspace setting it. Given that this code only
runs when userspace either can't (resume, gpu reset) or explicitly
won't(gem_init) touch the hw this shouldn't have an adverse effect.

Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f691e2f4

drivers/gpu/drm/i915/i915_gem.c

+4 −1
Original line number Diff line number Diff line
@@ -3685,13 +3685,16 @@ void i915_gem_init_swizzling(struct drm_device *dev) 
{

	drm_i915_private_t *dev_priv = dev->dev_private;



	if (INTEL_INFO(dev)->gen < 6 ||

	if (INTEL_INFO(dev)->gen < 5 ||

	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)

		return;



	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |

				 DISP_TILE_SURFACE_SWIZZLING);



	if (IS_GEN5(dev))

		return;



	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);

	if (IS_GEN6(dev))

		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));

drivers/gpu/drm/i915/intel_display.c

+0 −6
Original line number Diff line number Diff line
@@ -6029,12 +6029,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 


	intel_wait_for_vblank(dev, pipe);



	if (IS_GEN5(dev)) {

		/* enable address swizzle for tiling buffer */

		temp = I915_READ(DISP_ARB_CTL);

		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);

	}



	I915_WRITE(DSPCNTR(plane), dspcntr);

	POSTING_READ(DSPCNTR(plane));