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Commit f691e2f4 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: swizzling support for snb/ivb 



We have to do this manually. Somebody had a Great Idea.

I've measured speed-ups just a few percent above the noise level
(below 5% for the best case), but no slowdows. Chris Wilson measured
quite a bit more (10-20% above the usual snb variance) on a more
recent and better tuned version of sna, but also recorded a few
slow-downs on benchmarks know for uglier amounts of snb-induced
variance.

v2: Incorporate Ben Widawsky's preliminary review comments and
elaborate a bit about the performance impact in the changelog.

v3: Add a comment as to why we don't need to check the 3rd memory
channel.

v4: Fixup whitespace.

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 172975aa

drivers/gpu/drm/i915/i915_dma.c

+1 −1
Original line number Diff line number Diff line
@@ -1208,7 +1208,7 @@ static int i915_load_gem_init(struct drm_device *dev) 
	i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);



	mutex_lock(&dev->struct_mutex);

	ret = i915_gem_init_ringbuffer(dev);

	ret = i915_gem_init_hw(dev);

	mutex_unlock(&dev->struct_mutex);

	if (ret)

		return ret;

drivers/gpu/drm/i915/i915_drv.c

+3 −1
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ static int i915_drm_thaw(struct drm_device *dev) 
		mutex_lock(&dev->struct_mutex);

		dev_priv->mm.suspended = 0;



		error = i915_gem_init_ringbuffer(dev);

		error = i915_gem_init_hw(dev);

		mutex_unlock(&dev->struct_mutex);



		if (HAS_PCH_SPLIT(dev))
@@ -686,6 +686,8 @@ int i915_reset(struct drm_device *dev, u8 flags) 
			!dev_priv->mm.suspended) {

		dev_priv->mm.suspended = 0;



		i915_gem_init_swizzling(dev);



		dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);

		if (HAS_BSD(dev))

		    dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -1187,7 +1187,8 @@ int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 
					    uint32_t read_domains,

					    uint32_t write_domain);

int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);

int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);

int __must_check i915_gem_init_hw(struct drm_device *dev);

void i915_gem_init_swizzling(struct drm_device *dev);

void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

void i915_gem_do_init(struct drm_device *dev,

		      unsigned long start,

drivers/gpu/drm/i915/i915_gem.c

+21 −2
Original line number Diff line number Diff line
@@ -3681,12 +3681,31 @@ i915_gem_idle(struct drm_device *dev) 
	return 0;

}



void i915_gem_init_swizzling(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;



	if (INTEL_INFO(dev)->gen < 6 ||

	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)

		return;



	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |

				 DISP_TILE_SURFACE_SWIZZLING);



	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);

	if (IS_GEN6(dev))

		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));

	else

		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));

}

int

i915_gem_init_ringbuffer(struct drm_device *dev)

i915_gem_init_hw(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret;



	i915_gem_init_swizzling(dev);



	ret = intel_init_render_ring_buffer(dev);

	if (ret)

		return ret;
@@ -3742,7 +3761,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 
	mutex_lock(&dev->struct_mutex);

	dev_priv->mm.suspended = 0;



	ret = i915_gem_init_ringbuffer(dev);

	ret = i915_gem_init_hw(dev);

	if (ret != 0) {

		mutex_unlock(&dev->struct_mutex);

		return ret;

drivers/gpu/drm/i915/i915_gem_tiling.c

+17 −2
Original line number Diff line number Diff line
@@ -93,8 +93,23 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;



	if (INTEL_INFO(dev)->gen >= 6) {

		uint32_t dimm_c0, dimm_c1;

		dimm_c0 = I915_READ(MAD_DIMM_C0);

		dimm_c1 = I915_READ(MAD_DIMM_C1);

		dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;

		dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;

		/* Enable swizzling when the channels are populated with

		 * identically sized dimms. We don't need to check the 3rd

		 * channel because no cpu with gpu attached ships in that

		 * configuration. Also, swizzling only makes sense for 2

		 * channels anyway. */

		if (dimm_c0 == dimm_c1) {

			swizzle_x = I915_BIT_6_SWIZZLE_9_10;

			swizzle_y = I915_BIT_6_SWIZZLE_9;

		} else {

			swizzle_x = I915_BIT_6_SWIZZLE_NONE;

			swizzle_y = I915_BIT_6_SWIZZLE_NONE;

		}

	} else if (IS_GEN5(dev)) {

		/* On Ironlake whatever DRAM config, GPU always do

		 * same swizzling setup.