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Commit 0ed9f960 authored by Dhaval Patel's avatar Dhaval Patel Committed by Narendra Muppalla
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msm: mdss: fix pll stop sequence for msm8996 target 



Turning off pll digital block before link clocks leads
to clock status stuck ON. Ideally, DSI driver should
first stop the lanes, followed by link clock stop
and pll disable. This change implements these
recommended sequence for both DSI controllers.

Conflicts:
	drivers/video/fbdev/msm/msm_mdss_io_8974.c

Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
[narendram@codeaurora.org: remove fb driver dependency]
Signed-off-by: default avatarNarendra Muppalla <narendram@codeaurora.org>
parent 0d49d47b

drivers/clk/qcom/mdss/mdss-dsi-pll-8996-util.c

+13 −1
Original line number Diff line number Diff line
@@ -272,6 +272,7 @@ static void dsi_pll_disable(struct clk *c) 
{

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	struct mdss_pll_resources *pll = vco->priv;

	struct mdss_pll_resources *slave;



	if (!pll->pll_on &&

		mdss_pll_resource_enable(pll, true)) {
@@ -280,14 +281,25 @@ static void dsi_pll_disable(struct clk *c) 
	}



	pll->handoff_resources = false;

	slave = pll->slave;



	dsi_pll_stop_8996(pll->pll_base);



	/* stop pll output */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);

	/* stop clk */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);

	/* stop digital block */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);



	if (slave) {

		/* stop pll output */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);

		/* stop clk */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);

		/* stop digital block */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);

	}



	mdss_pll_resource_enable(pll, false);