Merge "msm: mdss: add configuration for dsi pll-1's clock dividers" into msm-4.8

- label:	       	A string used to describe the driver used.

- vcca-supply:		Phandle for vcca regulator device node.

- qcom,dsi-pll-slave:	indicates it is pll slave at split display case. Otherwise

			it is pll master.

- qcom,platform-supply-entries:	A node that lists the elements of the supply. There

				can be more than one instance of this binding,

				in which case the entry would be appended with

		clock-names = "mdp_core_clk", "iface_clk", "bus_clk";

		clock-rate = <0>, <0>, <0>;

		qcom,dsi-pll-slave;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

	pout = &pdb->out;

	/*

	 * postdiv = 1/2/4/8

	 * n1div = 1 - 15

	 * fot the time being, assume postdiv = 1

	 * vco rate = bit_clk * postdiv * n1div

	 * vco range from 1300 to 2600 Mhz

	 * postdiv = 1

	 * n1div = 1 to 15

	 * n1div = roundup(1300Mhz / bit_clk)

	 * support bit_clk above 86.67Mhz

	 */

	/* this is for vco/bit clock */

	struct mdss_pll_resources *pll = clk->priv;

	struct dsi_pll_db *pdb;

	struct dsi_pll_output *pout;

	struct mdss_pll_resources *slave;

	rc = mdss_pll_resource_enable(pll, true);

	if (rc) {

	n2div |= (div << 4);

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n2div);

	/* commit slave if split display is enabled */

	slave = pll->slave;

	if (slave)

		MDSS_PLL_REG_W(slave->pll_base, DSIPHY_CMN_CLK_CFG0, n2div);

	pout->pll_n2div = div;

	/* set dsiclk_sel=1 so that n2div *= 2 */

	u32 n2div;

	struct mdss_pll_resources *pll = clk->priv;

	if (is_gdsc_disabled(pll))

		return 0;

	rc = mdss_pll_resource_enable(pll, true);

	if (rc) {

		pr_err("Failed to enable mdss dsi pll resources\n");

				vco_clk_rate, fref);

	dec_start_multiple = div_s64(vco_clk_rate * multiplier, fref);

	div_s64_rem(dec_start_multiple, multiplier, &div_frac_start);

	div_s64_rem(vco_clk_rate * multiplier, fref, &div_frac_start);

	dec_start = div_s64(dec_start_multiple, multiplier);

	pout->plllock_cmp = (u32)pll_comp_val;

	pout->pll_txclk_en = 1;

	pout->pll_clkbuflr_en = 1;	/* right output */

	pout->cmn_ldo_cntrl = 0x1c;

}

	data = pout->pll_misc1;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_MISC1, data);

	data = pout->pll_ie_trim;

	data = pin->pll_ie_trim;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IE_TRIM, data);

	data = pout->pll_ip_trim;

	data = pin->pll_ip_trim;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IP_TRIM, data);

	data = ((pin->pll_cpmset_cur << 3) | pin->pll_cpcset_cur);

	data = ((pdb->in.pll_lpf_cap2 << 4) | pdb->in.pll_lpf_cap1);

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_LPF1, data);

	data = pout->pll_iptat_trim;

	data = pin->pll_iptat_trim;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IPTAT_TRIM, data);

	data = (pdb->in.pll_c3ctrl | (pdb->in.pll_r3ctrl << 4));

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DEC_START, data);

	data = pout->div_frac_start;

	data &= 0x0ff;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START1, data);

	data = (pout->div_frac_start >> 8);

	data &= 0x0ff;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START2, data);

	data = (pout->div_frac_start >> 16);

	data &= 0x0ff;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START3, data);

	data = pout->plllock_cmp;

	int rc;

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	struct mdss_pll_resources *pll = vco->priv;

	struct mdss_pll_resources *slave;

	struct dsi_pll_db *pdb;

	pdb = (struct dsi_pll_db *)pll->priv;

	pll_8996_calc_vco_count(pdb, pll->vco_current_rate,

					pll->vco_ref_clk_rate);

	/* commit slave if split display is enabled */

	slave = pll->slave;

	if (slave)

		pll_db_commit_8996(slave->pll_base, pdb);

	/* commit master itself */

	pll_db_commit_8996(pll->pll_base, pdb);

	mdss_pll_resource_enable(pll, false);

				struct mdss_pll_resources *pll_res)

{

	int rc;

	static struct mdss_pll_resources *master_pll;

	if (!pdev || !pdev->dev.of_node) {

		pr_err("Invalid input parameters\n");

		return -EPROBE_DEFER;

	}

	pll_res->priv = &pll_db;

	pr_debug("ndx=%d is_slave=%d\n", pll_res->index, pll_res->is_slave);

	if (!pll_res->is_slave) {

		/* master at split display or stand alone */

		pll_res->priv = &pll_db;

		master_pll = pll_res;	/* keep master pll */

	} else {

		/* slave pll */

		if (!master_pll) {

			pr_err("No match PLL master found for ndx=%d\n",

							pll_res->index);

			return -EINVAL;

		}

		master_pll->slave = pll_res;

		return 0;	/* done for slave */

	}

	/*

	 * Set client data to mux, div and vco clocks.

	 * This needs to be done only for PLL0 since, that is the one in

};

struct dsi_pll_output {

	u32 clkbuflr_en;	/* reg: 0x041c, unknown */

	u32 pll_txclk_en;	/* reg: 0x04c0 */

	u32 dec_start;		/* reg: 0x0490 */

	u32 div_frac_start;	/* reg: 0x04b4, 0x4b8, 0x04bc */

	u32 pll_resetsm_cntrl5;	/* reg: 0x043c */

	u32 pll_kvco_code;		/* reg: 0x0458 */

	u32 pll_ie_trim;	/* reg: 0x0400 */

	u32 pll_ip_trim;	/* reg: 0x0404 */

	u32 pll_iptat_trim;	/* reg: 0x0410 */

	u32 pll_clkbuflr_en;	/* reg: 0x001c */

	u32 cmn_clk_cfg0;	/* reg: 0x0010 */

	u32 cmn_clk_cfg1;	/* reg: 0x0014 */

	u32 cmn_ldo_cntrl;	/* reg: 0x004c */

		pll_res->index = 0;

	}

	pll_res->is_slave = of_property_read_bool(pdev->dev.of_node,

						"qcom,dsi-pll-slave");

	pll_base_reg = platform_get_resource_byname(pdev,

						IORESOURCE_MEM, "pll_base");

	if (!pll_base_reg) {