msm: mdss: add configuration for dsi pll-1's clock dividers

During split display case, pll-1 share vco output of pll-0.
Therefore pll-1's related clock dividers need to be
configured along with pll-0.

Change-Id: I98744ec0b8a5bea952f41754788ba44d824d3373
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>