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Commit 0b4fef02 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "coresight: tmc: Change ETR DDR transaction configuration" into msm-4.8

parents 352e357f cd303238

drivers/hwtracing/coresight/coresight-tmc-etr.c

+3 −0
Original line number Diff line number Diff line
@@ -43,6 +43,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) 
	axictl = (axictl &

		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |

		  TMC_AXICTL_PROT_CTL_B1;

	axictl = (axictl &

		  ~(TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1)) |

		  TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);



	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);

drivers/hwtracing/coresight/coresight-tmc.h

+2 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
/* TMC_AXICTL - 0x110 */

#define TMC_AXICTL_PROT_CTL_B0	BIT(0)

#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_CACHE_CTL_B0	BIT(2)

#define TMC_AXICTL_CACHE_CTL_B1	BIT(3)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_WR_BURST_16	0xF00

/* TMC_FFCR - 0x304 */