Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cd303238 authored by Satyajit Desai's avatar Satyajit Desai
Browse files

coresight: tmc: Change ETR DDR transaction configuration 



Set AXI control register on ETR to use normal non-cacheable
bufferable mode to meet bandwidth requirement. There is a
disconnect between the AXI protocol version on ETR versus the
rest of the system. The below table illustrates the correct
config to be used
-----------------------------------------------------------------
ARCACHE[1:0] | AWCACHE[1:0] | Memorytype
          00 |           00 | Device Non-bufferable
          01 |           01 | Device Bufferable
          10 |           10 | Normal Non-cacheable Non-bufferable
          11 |           11 | Normal Non-cacheable Bufferable
----------------------------------------------------------------

Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
Change-Id: I0c2255389641ede80702415b4083bfc9a46881be
parent e0d19e4c

drivers/hwtracing/coresight/coresight-tmc-etr.c

+3 −0
Original line number Diff line number Diff line
@@ -43,6 +43,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) 
	axictl = (axictl &

		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |

		  TMC_AXICTL_PROT_CTL_B1;

	axictl = (axictl &

		  ~(TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1)) |

		  TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);



	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);

drivers/hwtracing/coresight/coresight-tmc.h

+2 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
/* TMC_AXICTL - 0x110 */

#define TMC_AXICTL_PROT_CTL_B0	BIT(0)

#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_CACHE_CTL_B0	BIT(2)

#define TMC_AXICTL_CACHE_CTL_B1	BIT(3)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_WR_BURST_16	0xF00

/* TMC_FFCR - 0x304 */