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Commit 0a92eead authored by Rajesh Yadav's avatar Rajesh Yadav
Browse files

drm/msm/sde: Add support for dspp pa sixzone features 



Change adds support for dspp pa sixzone feature to
color processing module present in CRTC.

Change-Id: Ib957ae417d0199053758d97431356f7596887ec5
Signed-off-by: default avatarRajesh Yadav <ryadav@codeaurora.org>
parent 284947c2

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ 
		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-gamut = <0x1000 0x00040000>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

drivers/gpu/drm/msm/sde/sde_color_processing.c

+27 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ static void dspp_pcc_install_property(struct drm_crtc *crtc); 


static void dspp_hsic_install_property(struct drm_crtc *crtc);



static void dspp_sixzone_install_property(struct drm_crtc *crtc);



static void dspp_ad_install_property(struct drm_crtc *crtc);



static void dspp_vlut_install_property(struct drm_crtc *crtc);
@@ -81,6 +83,7 @@ static void sde_cp_ad_set_prop(struct sde_crtc *sde_crtc, 
do { \

	func[SDE_DSPP_PCC] = dspp_pcc_install_property; \

	func[SDE_DSPP_HSIC] = dspp_hsic_install_property; \

	func[SDE_DSPP_SIXZONE] = dspp_sixzone_install_property; \

	func[SDE_DSPP_AD] = dspp_ad_install_property; \

	func[SDE_DSPP_VLUT] = dspp_vlut_install_property; \

	func[SDE_DSPP_GAMUT] = dspp_gamut_install_property; \
@@ -1077,6 +1080,30 @@ static void dspp_hsic_install_property(struct drm_crtc *crtc) 
	}

}



static void dspp_sixzone_install_property(struct drm_crtc *crtc)

{

	char feature_name[256];

	struct sde_kms *kms = NULL;

	struct sde_mdss_cfg *catalog = NULL;

	u32 version;



	kms = get_kms(crtc);

	catalog = kms->catalog;

	version = catalog->dspp[0].sblk->sixzone.version >> 16;

	switch (version) {

	case 1:

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_SIXZONE_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_SIXZONE,

			sizeof(struct drm_msm_sixzone));

		break;

	default:

		DRM_ERROR("version %d not supported\n", version);

		break;

	}

}



static void dspp_vlut_install_property(struct drm_crtc *crtc)

{

	char feature_name[256];

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+11 −1
Original line number Diff line number Diff line
@@ -72,6 +72,10 @@ enum { 
#define PA_VAL_EN BIT(27)

#define PA_CONT_EN BIT(28)



#define PA_SIXZONE_HUE_EN BIT(29)

#define PA_SIXZONE_SAT_EN BIT(30)

#define PA_SIXZONE_VAL_EN BIT(31)



#define PA_HIST_EN BIT(16)



#define PA_SKIN_EN BIT(7)
@@ -87,11 +91,17 @@ enum { 
#define PA_SAT_OFF 0x20

#define PA_VAL_OFF 0x24

#define PA_CONT_OFF 0x28

#define PA_PWL_HOLD_OFF 0x40



#define PA_DISABLE_REQUIRED(x) \

	!((x) & (PA_SKIN_EN | PA_SKY_EN | \

	PA_FOL_EN | PA_HUE_EN | \

	PA_SAT_EN | PA_VAL_EN | \

	PA_CONT_EN | PA_HIST_EN))

	PA_CONT_EN | PA_HIST_EN | \

	PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN | \

	PA_SIXZONE_VAL_EN))



#define SIXZONE_ADJ_CURVE_P1_OFF 0x4

#define SIXZONE_THRESHOLDS_OFF 0x8



#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c

+82 −2
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#include "sde_hw_color_processing_v1_7.h"

#include "sde_hw_ctl.h"



#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))



#define PA_HUE_VIG_OFF		0x110

#define PA_SAT_VIG_OFF		0x114

#define PA_VAL_VIG_OFF		0x118
@@ -75,18 +77,23 @@ 
#define DSPP_OP_PA_FOL_EN	BIT(6)

#define DSPP_OP_PA_SKY_EN	BIT(7)



#define DSPP_SZ_ADJ_CURVE_P1_OFF	0x4

#define DSPP_SZ_THRESHOLDS_OFF	0x8

#define DSPP_PA_PWL_HOLD_OFF	0x40



#define PA_VIG_DISABLE_REQUIRED(x) \

			!((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \

			VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \

			VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \

			VIG_OP_PA_CONT_EN))





#define PA_DSPP_DISABLE_REQUIRED(x) \

			!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \

			DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \

			DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN))

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN | \

			DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN | \

			DSPP_OP_SZ_VAL_EN))



#define DSPP_OP_PCC_ENABLE	BIT(0)

#define PCC_OP_MODE_OFF		0
@@ -290,6 +297,79 @@ void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg) 
	__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic, cont, DSPP);

}



void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_sixzone *sixzone;

	u32 opcode = 0, local_opcode = 0;

	u32 reg = 0, hold = 0, local_hold = 0;

	u32 addr = 0;

	int i = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable sixzone feature\n");

		opcode &= ~(DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN |

			DSPP_OP_SZ_VAL_EN);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_sixzone));

		return;

	}



	sixzone = hw_cfg->payload;



	reg = BIT(26);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->sixzone.base, reg);



	addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_ADJ_CURVE_P1_OFF;

	for (i = 0; i < SIXZONE_LUT_SIZE; i++) {

		SDE_REG_WRITE(&ctx->hw, addr, sixzone->curve[i].p1);

		SDE_REG_WRITE(&ctx->hw, (addr - 4), sixzone->curve[i].p0);

	}



	addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_THRESHOLDS_OFF;

	SDE_REG_WRITE(&ctx->hw, addr, sixzone->threshold);

	SDE_REG_WRITE(&ctx->hw, (addr + 4), sixzone->adjust_p0);

	SDE_REG_WRITE(&ctx->hw, (addr + 8), sixzone->adjust_p1);



	hold = SDE_REG_READ(&ctx->hw,

		(ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF));

	local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);

	local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);

	hold &= ~REG_MASK_SHIFT(4, 12);

	hold |= local_hold;

	SDE_REG_WRITE(&ctx->hw,

		(ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF),

		hold);



	if (sixzone->flags & SIXZONE_HUE_ENABLE)

		local_opcode |= DSPP_OP_SZ_HUE_EN;

	if (sixzone->flags & SIXZONE_SAT_ENABLE)

		local_opcode |= DSPP_OP_SZ_SAT_EN;

	if (sixzone->flags & SIXZONE_VAL_ENABLE)

		local_opcode |= DSPP_OP_SZ_VAL_EN;



	if (local_opcode)

		local_opcode |= DSPP_OP_PA_EN;



	opcode &= ~REG_MASK_SHIFT(3, 29);

	opcode |= local_opcode;

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

}



void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,

				   enum sde_memcolor_type type,

				   void *cfg)

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h

+7 −0
Original line number Diff line number Diff line
@@ -68,6 +68,13 @@ void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg); 
 */

void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg);



/**

 * sde_setup_dspp_sixzone_v17 - setup DSPP sixzone feature in v1.7 hardware

 * @ctx: Pointer to DSPP context

 * @cfg: Pointer to sixzone data

 */

void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg);



/**

 * sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware

 * @ctx: Pointer to DSPP context