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Commit 284947c2 authored by Rajesh Yadav's avatar Rajesh Yadav
Browse files

drm/msm/sde: Add support for dspp pa hsic features 



Change adds support for dspp pa hsic feature to
color processing module present in CRTC.

Change-Id: I6c846df5812c4773edacdbba264fc23c078bce34
Signed-off-by: default avatarRajesh Yadav <ryadav@codeaurora.org>
parent c70d827b

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ 


		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-gamut = <0x1000 0x00040000>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

drivers/gpu/drm/msm/sde/sde_color_processing.c

+7 −31
Original line number Diff line number Diff line
@@ -103,10 +103,7 @@ enum { 
	SDE_CP_CRTC_DSPP_IGC,

	SDE_CP_CRTC_DSPP_PCC,

	SDE_CP_CRTC_DSPP_GC,

	SDE_CP_CRTC_DSPP_HUE,

	SDE_CP_CRTC_DSPP_SAT,

	SDE_CP_CRTC_DSPP_VAL,

	SDE_CP_CRTC_DSPP_CONT,

	SDE_CP_CRTC_DSPP_HSIC,

	SDE_CP_CRTC_DSPP_MEMCOLOR,

	SDE_CP_CRTC_DSPP_SIXZONE,

	SDE_CP_CRTC_DSPP_GAMUT,
@@ -583,33 +580,12 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, 
			}

			hw_dspp->ops.setup_gc(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_HUE:

			if (!hw_dspp || !hw_dspp->ops.setup_hue) {

		case SDE_CP_CRTC_DSPP_HSIC:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_hsic) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_hue(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_SAT:

			if (!hw_dspp || !hw_dspp->ops.setup_sat) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_sat(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_VAL:

			if (!hw_dspp || !hw_dspp->ops.setup_val) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_val(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_CONT:

			if (!hw_dspp || !hw_dspp->ops.setup_cont) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_cont(hw_dspp, &hw_cfg);

			hw_dspp->ops.setup_pa_hsic(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_MEMCOLOR:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor) {
@@ -1091,9 +1067,9 @@ static void dspp_hsic_install_property(struct drm_crtc *crtc) 
	switch (version) {

	case 1:

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_HUE_V", version);

		sde_cp_crtc_install_range_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_HUE, 0, U32_MAX, 0);

			"SDE_DSPP_PA_HSIC_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_HSIC, sizeof(struct drm_msm_pa_hsic));

		break;

	default:

		DRM_ERROR("version %d not supported\n", version);

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+28 −0
Original line number Diff line number Diff line
@@ -66,4 +66,32 @@ enum { 
#define PCC_GG_OFF 0x70

#define PCC_BB_OFF 0x7c



#define PA_EN BIT(20)

#define PA_HUE_EN BIT(25)

#define PA_SAT_EN BIT(26)

#define PA_VAL_EN BIT(27)

#define PA_CONT_EN BIT(28)



#define PA_HIST_EN BIT(16)



#define PA_SKIN_EN BIT(7)

#define PA_FOL_EN BIT(6)

#define PA_SKY_EN BIT(5)



#define PA_HUE_MASK (BIT(12) - 1)

#define PA_SAT_MASK (BIT(16) - 1)

#define PA_VAL_MASK (BIT(8) - 1)

#define PA_CONT_MASK (BIT(8) - 1)



#define PA_HUE_OFF 0x1c

#define PA_SAT_OFF 0x20

#define PA_VAL_OFF 0x24

#define PA_CONT_OFF 0x28



#define PA_DISABLE_REQUIRED(x) \

	!((x) & (PA_SKIN_EN | PA_SKY_EN | \

	PA_FOL_EN | PA_HUE_EN | \

	PA_SAT_EN | PA_VAL_EN | \

	PA_CONT_EN | PA_HIST_EN))



#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c

+76 −52
Original line number Diff line number Diff line
@@ -19,10 +19,10 @@ 
#define PA_VAL_VIG_OFF		0x118

#define PA_CONT_VIG_OFF		0x11C



#define PA_HUE_DSPP_OFF		0x238

#define PA_SAT_DSPP_OFF		0x23C

#define PA_VAL_DSPP_OFF		0x240

#define PA_CONT_DSPP_OFF	0x244

#define PA_HUE_DSPP_OFF		0x1c

#define PA_SAT_DSPP_OFF		0x20

#define PA_VAL_DSPP_OFF		0x24

#define PA_CONT_DSPP_OFF	0x28



#define PA_LUTV_DSPP_OFF	0x1400

#define PA_LUT_SWAP_OFF		0x234
@@ -70,6 +70,7 @@ 
#define DSPP_OP_PA_CONT_EN	BIT(28)

#define DSPP_OP_PA_EN		BIT(20)

#define DSPP_OP_PA_LUTV_EN	BIT(19)

#define DSPP_OP_PA_HIST_EN	BIT(16)

#define DSPP_OP_PA_SKIN_EN	BIT(5)

#define DSPP_OP_PA_FOL_EN	BIT(6)

#define DSPP_OP_PA_SKY_EN	BIT(7)
@@ -85,7 +86,7 @@ 
			!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \

			DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \

			DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN))



#define DSPP_OP_PCC_ENABLE	BIT(0)

#define PCC_OP_MODE_OFF		0
@@ -112,30 +113,27 @@ 




static void __setup_pa_hue(struct sde_hw_blk_reg_map *hw,

			const struct sde_pp_blk *blk, uint32_t hue,

			int location)

		const struct sde_pp_blk *blk, u32 hue, int loc)

{

	u32 base = blk->base;

	u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;

	u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :

					VIG_OP_PA_HUE_EN;

	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 offset = (loc == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;

	u32 op_hue_en = (loc == DSPP) ? DSPP_OP_PA_HUE_EN : VIG_OP_PA_HUE_EN;

	u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 disable_req;

	u32 opmode;



	SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);



	opmode = SDE_REG_READ(hw, base);

	SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);



	if (!hue) {

		opmode &= ~op_hue_en;

		disable_req = (location == DSPP) ?

		disable_req = (loc == DSPP) ?

			PA_DSPP_DISABLE_REQUIRED(opmode) :

			PA_VIG_DISABLE_REQUIRED(opmode);

		if (disable_req)

			opmode &= ~op_pa_en;

	} else {

		opmode |= op_hue_en | op_pa_en;

		opmode |= (op_hue_en | op_pa_en);

	}



	SDE_REG_WRITE(hw, base, opmode);
@@ -148,38 +146,28 @@ void sde_setup_pipe_pa_hue_v1_7(struct sde_hw_pipe *ctx, void *cfg) 
	__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);

}



void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg)

{

	uint32_t hue = *((uint32_t *)cfg);



	__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);

}



static void __setup_pa_sat(struct sde_hw_blk_reg_map *hw,

			const struct sde_pp_blk *blk, uint32_t sat,

			int location)

		const struct sde_pp_blk *blk, u32 sat, int loc)

{

	u32 base = blk->base;

	u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;

	u32 op_sat_en = (location == DSPP) ?

			DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;

	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 offset = (loc == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;

	u32 op_sat_en = (loc == DSPP) ? DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;

	u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 disable_req;

	u32 opmode;



	SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);



	opmode = SDE_REG_READ(hw, base);

	SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);



	if (!sat) {

		opmode &= ~op_sat_en;

		disable_req = (location == DSPP) ?

		disable_req = (loc == DSPP) ?

			PA_DSPP_DISABLE_REQUIRED(opmode) :

			PA_VIG_DISABLE_REQUIRED(opmode);

		if (disable_req)

			opmode &= ~op_pa_en;

	} else {

		opmode |= op_sat_en | op_pa_en;

		opmode |= (op_sat_en | op_pa_en);

	}



	SDE_REG_WRITE(hw, base, opmode);
@@ -193,30 +181,27 @@ void sde_setup_pipe_pa_sat_v1_7(struct sde_hw_pipe *ctx, void *cfg) 
}



static void __setup_pa_val(struct sde_hw_blk_reg_map *hw,

			const struct sde_pp_blk *blk, uint32_t value,

			int location)

		const struct sde_pp_blk *blk, u32 value, int loc)

{

	u32 base = blk->base;

	u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;

	u32 op_val_en = (location == DSPP) ?

			DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;

	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 offset = (loc == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;

	u32 op_val_en = (loc == DSPP) ? DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;

	u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 disable_req;

	u32 opmode;



	SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);



	opmode = SDE_REG_READ(hw, base);

	SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);



	if (!value) {

		opmode &= ~op_val_en;

		disable_req = (location == DSPP) ?

		disable_req = (loc == DSPP) ?

			PA_DSPP_DISABLE_REQUIRED(opmode) :

			PA_VIG_DISABLE_REQUIRED(opmode);

		if (disable_req)

			opmode &= ~op_pa_en;

	} else {

		opmode |= op_val_en | op_pa_en;

		opmode |= (op_val_en | op_pa_en);

	}



	SDE_REG_WRITE(hw, base, opmode);
@@ -230,30 +215,28 @@ void sde_setup_pipe_pa_val_v1_7(struct sde_hw_pipe *ctx, void *cfg) 
}



static void __setup_pa_cont(struct sde_hw_blk_reg_map *hw,

			const struct sde_pp_blk *blk, uint32_t contrast,

			int location)

		const struct sde_pp_blk *blk, u32 contrast, int loc)

{

	u32 base = blk->base;

	u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;

	u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :

					VIG_OP_PA_CONT_EN;

	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 offset = (loc == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;

	u32 op_cont_en = (loc == DSPP) ?

		DSPP_OP_PA_CONT_EN : VIG_OP_PA_CONT_EN;

	u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;

	u32 disable_req;

	u32 opmode;



	SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);



	opmode = SDE_REG_READ(hw, base);

	SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);



	if (!contrast) {

		opmode &= ~op_cont_en;

		disable_req = (location == DSPP) ?

		disable_req = (loc == DSPP) ?

			PA_DSPP_DISABLE_REQUIRED(opmode) :

			PA_VIG_DISABLE_REQUIRED(opmode);

		if (disable_req)

			opmode &= ~op_pa_en;

	} else {

		opmode |= op_cont_en | op_pa_en;

		opmode |= (op_cont_en | op_pa_en);

	}



	SDE_REG_WRITE(hw, base, opmode);
@@ -266,6 +249,47 @@ void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg) 
	__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);

}



void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_pa_hsic *hsic_cfg;

	u32 hue = 0;

	u32 sat = 0;

	u32 val = 0;

	u32 cont = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	if (hw_cfg->payload &&

		(hw_cfg->len != sizeof(struct drm_msm_pa_hsic))) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_pa_hsic));

		return;

	}



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable pa hsic feature\n");

	} else {

		hsic_cfg = hw_cfg->payload;

		if (hsic_cfg->flags & PA_HSIC_HUE_ENABLE)

			hue = hsic_cfg->hue;

		if (hsic_cfg->flags & PA_HSIC_SAT_ENABLE)

			sat = hsic_cfg->saturation;

		if (hsic_cfg->flags & PA_HSIC_VAL_ENABLE)

			val = hsic_cfg->value;

		if (hsic_cfg->flags & PA_HSIC_CONT_ENABLE)

			cont = hsic_cfg->contrast;

	}



	__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);

	__setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic, sat, DSPP);

	__setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic, val, DSPP);

	__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic, cont, DSPP);

}



void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,

				   enum sde_memcolor_type type,

				   void *cfg)

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h

+3 −3
Original line number Diff line number Diff line
@@ -62,11 +62,11 @@ void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx, 
void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg);



/**

 * sde_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware

 * sde_setup_dspp_pa_hsic_v17 - setup DSPP hsic feature in v1.7 hardware

 * @ctx: Pointer to DSPP context

 * @cfg: Pointer to hue data

 * @cfg: Pointer to hsic data

 */

void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg);

void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg);



/**

 * sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware