Loading drivers/mmc/host/sdhci-msm.c +8 −0 Original line number Diff line number Diff line Loading @@ -65,6 +65,10 @@ #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c #define CORE_8_BIT_SUPPORT (1 << 18) #define CORE_3_0V_SUPPORT (1 << 25) #define CDR_SELEXT_SHIFT 20 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) #define CMUX_SHIFT_PHASE_SHIFT 24 Loading Loading @@ -627,6 +631,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); writel_relaxed((readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | CORE_3_0V_SUPPORT | CORE_8_BIT_SUPPORT), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> Loading Loading
drivers/mmc/host/sdhci-msm.c +8 −0 Original line number Diff line number Diff line Loading @@ -65,6 +65,10 @@ #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c #define CORE_8_BIT_SUPPORT (1 << 18) #define CORE_3_0V_SUPPORT (1 << 25) #define CDR_SELEXT_SHIFT 20 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) #define CMUX_SHIFT_PHASE_SHIFT 24 Loading Loading @@ -627,6 +631,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); writel_relaxed((readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | CORE_3_0V_SUPPORT | CORE_8_BIT_SUPPORT), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> Loading