Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0097852c authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-for-4.7' of... 

Merge tag 'irqchip-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for Linux 4.7 from Marc Zyngier

- Layerscape SCFG MSI controller support
- LPC32xx interrupt controller support
- RPi irqchip support on arm64
- GICv2 cleanup
- GICv2 and GICv3 bug fixes
parents 9d9b7eed a1dcbd11

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

0 → 100644
+30 −0
Original line number Diff line number Diff line 
* Freescale Layerscape SCFG PCIe MSI controller



Required properties:



- compatible: should be "fsl,<soc-name>-msi" to identify

	      Layerscape PCIe MSI controller block such as:

              "fsl,1s1021a-msi"

              "fsl,1s1043a-msi"

- msi-controller: indicates that this is a PCIe MSI controller node

- reg: physical base address of the controller and length of memory mapped.

- interrupts: an interrupt to the parent interrupt controller.



Optional properties:

- interrupt-parent: the phandle to the parent interrupt controller.



This interrupt controller hardware is a second level interrupt controller that

is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based

platforms. If interrupt-parent is not provided, the default parent interrupt

controller will be used.

Each PCIe node needs to have property msi-parent that points to

MSI controller node



Examples:



	msi1: msi-controller@1571000 {

		compatible = "fsl,1s1043a-msi";

		reg = <0x0 0x1571000 0x0 0x8>,

		msi-controller;

		interrupts = <0 116 0x4>;

	};

arch/arm/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -531,6 +531,8 @@ config ARCH_LPC32XX 
	select COMMON_CLK

	select CPU_ARM926T

	select GENERIC_CLOCKEVENTS

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ

	select USE_OF

	help

	  Support for the NXP LPC32XX family of processors

arch/arm/mach-lpc32xx/phy3250.c

+0 −1
Original line number Diff line number Diff line
@@ -206,7 +206,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = { 
DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")

	.atag_offset	= 0x100,

	.map_io		= lpc32xx_map_io,

	.init_irq	= lpc32xx_init_irq,

	.init_machine	= lpc3250_machine_init,

	.dt_compat	= lpc32xx_dt_compat,

MACHINE_END

drivers/irqchip/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -246,5 +246,10 @@ config MVEBU_ODMI 
	bool

	select GENERIC_MSI_IRQ_DOMAIN



config LS_SCFG_MSI

	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE

	depends on PCI && PCI_MSI

	select PCI_MSI_IRQ_DOMAIN



config PARTITION_PERCPU

	bool

drivers/irqchip/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 
obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o

obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o

obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o

obj-$(CONFIG_ARCH_LPC32XX)		+= irq-lpc32xx.o

obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o

obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o

obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o
@@ -66,3 +67,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o 
obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o

obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o

obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o

obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o