Loading libpixelflinger/codeflinger/CodeCache.cpp +1 −5 Original line number Diff line number Diff line Loading @@ -201,13 +201,9 @@ int CodeCache::cache( const AssemblyKeyBase& keyBase, mCacheInUse += assemblySize; mWhen++; // synchronize caches... #if defined(__arm__) || defined(__mips__) || defined(__aarch64__) const long base = long(assembly->base()); const long curr = base + long(assembly->size()); err = cacheflush(base, curr, 0); ALOGE_IF(err, "cacheflush error %s\n", strerror(errno)); #endif __builtin___clear_cache((void*)base, (void*)curr); } pthread_mutex_unlock(&mLock); Loading libpixelflinger/tests/arch-arm64/assembler/arm64_assembler_test.cpp +2 −2 Original line number Diff line number Diff line Loading @@ -405,11 +405,11 @@ dataTransferTest_t dataTransferTests [] = }; int flushcache() void flushcache() { const long base = long(instrMem); const long curr = base + long(instrMemSize); return cacheflush(base, curr, 0); __builtin___clear_cache((void*)base, (void*)curr); } void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0, uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) Loading Loading
libpixelflinger/codeflinger/CodeCache.cpp +1 −5 Original line number Diff line number Diff line Loading @@ -201,13 +201,9 @@ int CodeCache::cache( const AssemblyKeyBase& keyBase, mCacheInUse += assemblySize; mWhen++; // synchronize caches... #if defined(__arm__) || defined(__mips__) || defined(__aarch64__) const long base = long(assembly->base()); const long curr = base + long(assembly->size()); err = cacheflush(base, curr, 0); ALOGE_IF(err, "cacheflush error %s\n", strerror(errno)); #endif __builtin___clear_cache((void*)base, (void*)curr); } pthread_mutex_unlock(&mLock); Loading
libpixelflinger/tests/arch-arm64/assembler/arm64_assembler_test.cpp +2 −2 Original line number Diff line number Diff line Loading @@ -405,11 +405,11 @@ dataTransferTest_t dataTransferTests [] = }; int flushcache() void flushcache() { const long base = long(instrMem); const long curr = base + long(instrMemSize); return cacheflush(base, curr, 0); __builtin___clear_cache((void*)base, (void*)curr); } void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0, uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) Loading