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Originally, if TARGET_ARCH_VARIANT is x86-atom, the SSE2 enhanced memset is used. This patch extends this to all x86 processors which support SSE2 (i.e. ARCH_X86_HAVE_SSE2 is true). Indentation added to the ifeq cases to make this easier to read. Change-Id: I05f49e237a95359d3f2e3216b037e3fc1a0fbcb0 Signed-off-by:Daniel Leung <daniel.leung@intel.com> Signed-off-by:
Andrew Boie <andrew.p.boie@intel.com>