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Commit 319af5e1 authored by Elliott Hughes's avatar Elliott Hughes Committed by Automerger Merge Worker
Browse files

Merge "riscv64: fix debuggerd_test build." am: 3b1e71c6 am: 8c27dc6b am: 97f766c9 

Original change: https://android-review.googlesource.com/c/platform/system/core/+/2498756



Change-Id: I0b019e2a98e5405489d53dc9d145a2734273118c
Signed-off-by: default avatarAutomerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
parents 4dc2ee31 97f766c9

debuggerd/Android.bp

+3 −0
Original line number Original line Diff line number Diff line
@@ -510,6 +510,9 @@ prebuilt_etc { 
        arm64: {

        arm64: {

            src: "seccomp_policy/crash_dump.arm.policy",

            src: "seccomp_policy/crash_dump.arm.policy",

        },

        },

        riscv64: {

            enabled: false,

        },

        x86: {

        x86: {

            src: "seccomp_policy/crash_dump.x86_64.policy",

            src: "seccomp_policy/crash_dump.x86_64.policy",

        },

        },

debuggerd/debuggerd_test.cpp

+19 −12
Original line number Original line Diff line number Diff line
@@ -2437,35 +2437,42 @@ TEST_F(CrasherTest, verify_dex_pc_with_function_name) { 
#if defined(__arm__)

#if defined(__arm__)

    asm volatile(

    asm volatile(

        "mov r1, %[base]\n"

        "mov r1, %[base]\n"

        "mov r2, 0\n"

        "mov r2, #0\n"

        "str r3, [r2]\n"

        "str r2, [r2]\n"

        : [base] "+r"(ptr)

        : [base] "+r"(ptr)

        :

        :

        : "r1", "r2", "r3", "memory");

        : "r1", "r2", "memory");

#elif defined(__aarch64__)

#elif defined(__aarch64__)

    asm volatile(

    asm volatile(

        "mov x1, %[base]\n"

        "mov x1, %[base]\n"

        "mov x2, 0\n"

        "mov x2, #0\n"

        "str x3, [x2]\n"

        "str xzr, [x2]\n"

        : [base] "+r"(ptr)

        : [base] "+r"(ptr)

        :

        :

        : "x1", "x2", "x3", "memory");

        : "x1", "x2", "memory");

#elif defined(__riscv)

    // TODO: x1 is ra (the link register) on riscv64, so this might have

    // unintended consequences, but we'll need to change the .cfi_escape if so.

    asm volatile(

        "mv x1, %[base]\n"

        "sw zero, 0(zero)\n"

        : [base] "+r"(ptr)

        :

        : "x1", "memory");

#elif defined(__i386__)

#elif defined(__i386__)

    asm volatile(

    asm volatile(

        "mov %[base], %%ecx\n"

        "mov %[base], %%ecx\n"

        "movl $0, %%edi\n"

        "movl $0, 0\n"

        "movl 0(%%edi), %%edx\n"

        : [base] "+r"(ptr)

        : [base] "+r"(ptr)

        :

        :

        : "edi", "ecx", "edx", "memory");

        : "ecx", "memory");

#elif defined(__x86_64__)

#elif defined(__x86_64__)

    asm volatile(

    asm volatile(

        "mov %[base], %%rdx\n"

        "mov %[base], %%rdx\n"

        "movq 0, %%rdi\n"

        "movq $0, 0\n"

        "movq 0(%%rdi), %%rcx\n"

        : [base] "+r"(ptr)

        : [base] "+r"(ptr)

        :

        :

        : "rcx", "rdx", "rdi", "memory");

        : "rdx", "memory");

#else

#else

#error "Unsupported architecture"

#error "Unsupported architecture"

#endif

#endif