Loading system/stack/acl/acl.h +11 −11 Original line number Diff line number Diff line Loading @@ -78,6 +78,17 @@ typedef struct { uint8_t role; /* HCI_ROLE_CENTRAL or HCI_ROLE_PERIPHERAL */ } tBTM_ROLE_SWITCH_CMPL; typedef struct { bool chg_ind; tBTM_PM_PWR_MD req_mode[BTM_MAX_PM_RECORDS + 1]; tBTM_PM_PWR_MD set_mode; tBTM_PM_STATE state; uint16_t interval; uint16_t max_lat; uint16_t min_loc_to; uint16_t min_rmt_to; } tBTM_PM_MCB; typedef struct { BD_FEATURES peer_le_features; bool peer_le_features_valid; Loading Loading @@ -234,17 +245,6 @@ inline std::string power_mode_state_text(tBTM_PM_STATE state) { } } typedef struct { bool chg_ind; tBTM_PM_PWR_MD req_mode[BTM_MAX_PM_RECORDS + 1]; tBTM_PM_PWR_MD set_mode; tBTM_PM_STATE state; uint16_t interval; uint16_t max_lat; uint16_t min_loc_to; uint16_t min_rmt_to; } tBTM_PM_MCB; /**************************************************** ** ACL Management API ****************************************************/ Loading Loading
system/stack/acl/acl.h +11 −11 Original line number Diff line number Diff line Loading @@ -78,6 +78,17 @@ typedef struct { uint8_t role; /* HCI_ROLE_CENTRAL or HCI_ROLE_PERIPHERAL */ } tBTM_ROLE_SWITCH_CMPL; typedef struct { bool chg_ind; tBTM_PM_PWR_MD req_mode[BTM_MAX_PM_RECORDS + 1]; tBTM_PM_PWR_MD set_mode; tBTM_PM_STATE state; uint16_t interval; uint16_t max_lat; uint16_t min_loc_to; uint16_t min_rmt_to; } tBTM_PM_MCB; typedef struct { BD_FEATURES peer_le_features; bool peer_le_features_valid; Loading Loading @@ -234,17 +245,6 @@ inline std::string power_mode_state_text(tBTM_PM_STATE state) { } } typedef struct { bool chg_ind; tBTM_PM_PWR_MD req_mode[BTM_MAX_PM_RECORDS + 1]; tBTM_PM_PWR_MD set_mode; tBTM_PM_STATE state; uint16_t interval; uint16_t max_lat; uint16_t min_loc_to; uint16_t min_rmt_to; } tBTM_PM_MCB; /**************************************************** ** ACL Management API ****************************************************/ Loading