Loading system/stack/include/hcidefs.h +1 −1 Original line number Diff line number Diff line Loading @@ -930,7 +930,7 @@ typedef struct { #define HCI_UNISOC_ACL_HIGH_PRIORITY 0xFF /* Parameter information for HCI_MTK_SET_ACL_PRIORITY */ #define HCI_MTK_ACL_PRIORITY_PARAM_SIZE 1 #define HCI_MTK_ACL_PRIORITY_PARAM_SIZE 4 #define HCI_MTK_SET_ACL_PRIORITY (0xFD95 | HCI_GRP_VENDOR_SPECIFIC) #define HCI_MTK_ACL_NORMAL_PRIORITY 0x00 #define HCI_MTK_ACL_HIGH_PRIORITY 0x01 Loading system/stack/l2cap/l2c_utils.cc +32 −32 Original line number Diff line number Diff line Loading @@ -2340,34 +2340,6 @@ static void l2cu_set_acl_priority_unisoc(tL2C_LCB* p_lcb, HCI_UNISOC_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_priority_latency_mtk * * Description Sends a VSC to set the ACL priority and recorded latency on * Mediatek chip. * * Returns void * ******************************************************************************/ static void l2cu_set_acl_priority_latency_mtk(tL2C_LCB* p_lcb, tL2CAP_PRIORITY priority) { uint8_t vs_param; if (priority == L2CAP_PRIORITY_HIGH) { // priority to high, if using latency mode check preset latency log::info("Set ACL priority: High Priority Mode"); vs_param = HCI_MTK_ACL_HIGH_PRIORITY; } else { // priority to normal log::info("Set ACL priority: Normal Mode"); vs_param = HCI_MTK_ACL_NORMAL_PRIORITY; } BTM_VendorSpecificCommand(HCI_MTK_SET_ACL_PRIORITY, HCI_MTK_ACL_PRIORITY_PARAM_SIZE, &vs_param, NULL); } /******************************************************************************* * * Function l2cu_set_acl_priority Loading Loading @@ -2413,10 +2385,6 @@ bool l2cu_set_acl_priority(const RawAddress& bd_addr, tL2CAP_PRIORITY priority, l2cu_set_acl_priority_unisoc(p_lcb, priority); break; case LMP_COMPID_MEDIATEK: l2cu_set_acl_priority_latency_mtk(p_lcb, priority); break; default: /* Not supported/required for other vendors */ break; Loading Loading @@ -2484,6 +2452,34 @@ static void l2cu_set_acl_latency_syna(tL2C_LCB* p_lcb, tL2CAP_LATENCY latency) { HCI_SYNA_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_latency_mtk * * Description Sends a VSC to set the ACL latency on Mediatek chip. * * Returns void * ******************************************************************************/ static void l2cu_set_acl_latency_mtk(tL2CAP_LATENCY latency) { log::info("Set ACL latency: {}", latency == L2CAP_LATENCY_LOW ? "Low Latancy" : "Normal Latency"); uint8_t command[HCI_MTK_ACL_PRIORITY_PARAM_SIZE]; uint8_t* pp = command; uint8_t vs_param = latency == L2CAP_LATENCY_LOW ? HCI_MTK_ACL_HIGH_PRIORITY : HCI_MTK_ACL_NORMAL_PRIORITY; UINT8_TO_STREAM(pp, vs_param); UINT8_TO_STREAM(pp, 0); UINT16_TO_STREAM(pp, 0); //reserved bytes BTM_VendorSpecificCommand(HCI_MTK_SET_ACL_PRIORITY, HCI_MTK_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_latency Loading Loading @@ -2516,6 +2512,10 @@ bool l2cu_set_acl_latency(const RawAddress& bd_addr, tL2CAP_LATENCY latency) { l2cu_set_acl_latency_syna(p_lcb, latency); break; case LMP_COMPID_MEDIATEK: l2cu_set_acl_latency_mtk(latency); break; default: /* Not supported/required for other vendors */ break; Loading Loading
system/stack/include/hcidefs.h +1 −1 Original line number Diff line number Diff line Loading @@ -930,7 +930,7 @@ typedef struct { #define HCI_UNISOC_ACL_HIGH_PRIORITY 0xFF /* Parameter information for HCI_MTK_SET_ACL_PRIORITY */ #define HCI_MTK_ACL_PRIORITY_PARAM_SIZE 1 #define HCI_MTK_ACL_PRIORITY_PARAM_SIZE 4 #define HCI_MTK_SET_ACL_PRIORITY (0xFD95 | HCI_GRP_VENDOR_SPECIFIC) #define HCI_MTK_ACL_NORMAL_PRIORITY 0x00 #define HCI_MTK_ACL_HIGH_PRIORITY 0x01 Loading
system/stack/l2cap/l2c_utils.cc +32 −32 Original line number Diff line number Diff line Loading @@ -2340,34 +2340,6 @@ static void l2cu_set_acl_priority_unisoc(tL2C_LCB* p_lcb, HCI_UNISOC_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_priority_latency_mtk * * Description Sends a VSC to set the ACL priority and recorded latency on * Mediatek chip. * * Returns void * ******************************************************************************/ static void l2cu_set_acl_priority_latency_mtk(tL2C_LCB* p_lcb, tL2CAP_PRIORITY priority) { uint8_t vs_param; if (priority == L2CAP_PRIORITY_HIGH) { // priority to high, if using latency mode check preset latency log::info("Set ACL priority: High Priority Mode"); vs_param = HCI_MTK_ACL_HIGH_PRIORITY; } else { // priority to normal log::info("Set ACL priority: Normal Mode"); vs_param = HCI_MTK_ACL_NORMAL_PRIORITY; } BTM_VendorSpecificCommand(HCI_MTK_SET_ACL_PRIORITY, HCI_MTK_ACL_PRIORITY_PARAM_SIZE, &vs_param, NULL); } /******************************************************************************* * * Function l2cu_set_acl_priority Loading Loading @@ -2413,10 +2385,6 @@ bool l2cu_set_acl_priority(const RawAddress& bd_addr, tL2CAP_PRIORITY priority, l2cu_set_acl_priority_unisoc(p_lcb, priority); break; case LMP_COMPID_MEDIATEK: l2cu_set_acl_priority_latency_mtk(p_lcb, priority); break; default: /* Not supported/required for other vendors */ break; Loading Loading @@ -2484,6 +2452,34 @@ static void l2cu_set_acl_latency_syna(tL2C_LCB* p_lcb, tL2CAP_LATENCY latency) { HCI_SYNA_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_latency_mtk * * Description Sends a VSC to set the ACL latency on Mediatek chip. * * Returns void * ******************************************************************************/ static void l2cu_set_acl_latency_mtk(tL2CAP_LATENCY latency) { log::info("Set ACL latency: {}", latency == L2CAP_LATENCY_LOW ? "Low Latancy" : "Normal Latency"); uint8_t command[HCI_MTK_ACL_PRIORITY_PARAM_SIZE]; uint8_t* pp = command; uint8_t vs_param = latency == L2CAP_LATENCY_LOW ? HCI_MTK_ACL_HIGH_PRIORITY : HCI_MTK_ACL_NORMAL_PRIORITY; UINT8_TO_STREAM(pp, vs_param); UINT8_TO_STREAM(pp, 0); UINT16_TO_STREAM(pp, 0); //reserved bytes BTM_VendorSpecificCommand(HCI_MTK_SET_ACL_PRIORITY, HCI_MTK_ACL_PRIORITY_PARAM_SIZE, command, NULL); } /******************************************************************************* * * Function l2cu_set_acl_latency Loading Loading @@ -2516,6 +2512,10 @@ bool l2cu_set_acl_latency(const RawAddress& bd_addr, tL2CAP_LATENCY latency) { l2cu_set_acl_latency_syna(p_lcb, latency); break; case LMP_COMPID_MEDIATEK: l2cu_set_acl_latency_mtk(latency); break; default: /* Not supported/required for other vendors */ break; Loading