Loading system/stack/l2cap/l2c_api.cc +3 −1 Original line number Diff line number Diff line Loading @@ -1576,7 +1576,9 @@ uint16_t L2CA_FlushChannel(uint16_t lcid, uint16_t num_to_flush) { /* Cannot flush eRTM buffers once they have a sequence number */ if (p_ccb->peer_cfg.fcr.mode != L2CAP_FCR_ERTM_MODE) { const controller_t* controller = controller_get_interface(); if (num_to_flush != L2CAP_FLUSH_CHANS_GET) { // Don't need send enhanced_flush to controller if it is LE transport. if (p_lcb->transport != BT_TRANSPORT_LE && num_to_flush != L2CAP_FLUSH_CHANS_GET) { /* If the controller supports enhanced flush, flush the data queued at the * controller */ if (controller->supports_non_flushable_pb() && Loading Loading
system/stack/l2cap/l2c_api.cc +3 −1 Original line number Diff line number Diff line Loading @@ -1576,7 +1576,9 @@ uint16_t L2CA_FlushChannel(uint16_t lcid, uint16_t num_to_flush) { /* Cannot flush eRTM buffers once they have a sequence number */ if (p_ccb->peer_cfg.fcr.mode != L2CAP_FCR_ERTM_MODE) { const controller_t* controller = controller_get_interface(); if (num_to_flush != L2CAP_FLUSH_CHANS_GET) { // Don't need send enhanced_flush to controller if it is LE transport. if (p_lcb->transport != BT_TRANSPORT_LE && num_to_flush != L2CAP_FLUSH_CHANS_GET) { /* If the controller supports enhanced flush, flush the data queued at the * controller */ if (controller->supports_non_flushable_pb() && Loading