Loading services/surfaceflinger/Scheduler/VSyncReactor.cpp +3 −1 Original line number Diff line number Diff line Loading @@ -278,7 +278,9 @@ bool VSyncReactor::periodConfirmed(nsecs_t vsync_timestamp, std::optional<nsecs_ return false; } if (mSupportKernelIdleTimer) { const bool periodIsChanging = mPeriodTransitioningTo && (*mPeriodTransitioningTo != getPeriod()); if (mSupportKernelIdleTimer && !periodIsChanging) { // Clear out the Composer-provided period and use the allowance logic below HwcVsyncPeriod = {}; } Loading services/surfaceflinger/tests/unittests/VSyncReactorTest.cpp +19 −4 Original line number Diff line number Diff line Loading @@ -672,15 +672,30 @@ TEST_F(VSyncReactorTest, periodIsMeasuredIfIgnoringComposer) { kPendingLimit, true /* supportKernelIdleTimer */); bool periodFlushed = true; EXPECT_CALL(*mMockTracker, addVsyncTimestamp(_)).Times(2); EXPECT_CALL(*mMockTracker, addVsyncTimestamp(_)).Times(5); idleReactor.setIgnorePresentFences(true); // First, set the same period, which should only be confirmed when we receive two // matching callbacks idleReactor.setPeriod(10000); EXPECT_TRUE(idleReactor.addResyncSample(0, 0, &periodFlushed)); EXPECT_FALSE(periodFlushed); // Correct period but incorrect timestamp delta EXPECT_TRUE(idleReactor.addResyncSample(0, 10000, &periodFlushed)); EXPECT_FALSE(periodFlushed); // Correct period and correct timestamp delta EXPECT_FALSE(idleReactor.addResyncSample(10000, 10000, &periodFlushed)); EXPECT_TRUE(periodFlushed); // Then, set a new period, which should be confirmed as soon as we receive a callback // reporting the new period nsecs_t const newPeriod = 5000; idleReactor.setPeriod(newPeriod); EXPECT_TRUE(idleReactor.addResyncSample(0, 0, &periodFlushed)); // Incorrect timestamp delta and period EXPECT_TRUE(idleReactor.addResyncSample(20000, 10000, &periodFlushed)); EXPECT_FALSE(periodFlushed); EXPECT_FALSE(idleReactor.addResyncSample(newPeriod, 0, &periodFlushed)); // Incorrect timestamp delta but correct period EXPECT_FALSE(idleReactor.addResyncSample(20000, 5000, &periodFlushed)); EXPECT_TRUE(periodFlushed); EXPECT_TRUE(idleReactor.addPresentFence(generateSignalledFenceWithTime(0))); Loading Loading
services/surfaceflinger/Scheduler/VSyncReactor.cpp +3 −1 Original line number Diff line number Diff line Loading @@ -278,7 +278,9 @@ bool VSyncReactor::periodConfirmed(nsecs_t vsync_timestamp, std::optional<nsecs_ return false; } if (mSupportKernelIdleTimer) { const bool periodIsChanging = mPeriodTransitioningTo && (*mPeriodTransitioningTo != getPeriod()); if (mSupportKernelIdleTimer && !periodIsChanging) { // Clear out the Composer-provided period and use the allowance logic below HwcVsyncPeriod = {}; } Loading
services/surfaceflinger/tests/unittests/VSyncReactorTest.cpp +19 −4 Original line number Diff line number Diff line Loading @@ -672,15 +672,30 @@ TEST_F(VSyncReactorTest, periodIsMeasuredIfIgnoringComposer) { kPendingLimit, true /* supportKernelIdleTimer */); bool periodFlushed = true; EXPECT_CALL(*mMockTracker, addVsyncTimestamp(_)).Times(2); EXPECT_CALL(*mMockTracker, addVsyncTimestamp(_)).Times(5); idleReactor.setIgnorePresentFences(true); // First, set the same period, which should only be confirmed when we receive two // matching callbacks idleReactor.setPeriod(10000); EXPECT_TRUE(idleReactor.addResyncSample(0, 0, &periodFlushed)); EXPECT_FALSE(periodFlushed); // Correct period but incorrect timestamp delta EXPECT_TRUE(idleReactor.addResyncSample(0, 10000, &periodFlushed)); EXPECT_FALSE(periodFlushed); // Correct period and correct timestamp delta EXPECT_FALSE(idleReactor.addResyncSample(10000, 10000, &periodFlushed)); EXPECT_TRUE(periodFlushed); // Then, set a new period, which should be confirmed as soon as we receive a callback // reporting the new period nsecs_t const newPeriod = 5000; idleReactor.setPeriod(newPeriod); EXPECT_TRUE(idleReactor.addResyncSample(0, 0, &periodFlushed)); // Incorrect timestamp delta and period EXPECT_TRUE(idleReactor.addResyncSample(20000, 10000, &periodFlushed)); EXPECT_FALSE(periodFlushed); EXPECT_FALSE(idleReactor.addResyncSample(newPeriod, 0, &periodFlushed)); // Incorrect timestamp delta but correct period EXPECT_FALSE(idleReactor.addResyncSample(20000, 5000, &periodFlushed)); EXPECT_TRUE(periodFlushed); EXPECT_TRUE(idleReactor.addPresentFence(generateSignalledFenceWithTime(0))); Loading