Commit 2aff6c11 authored Apr 12, 2023 by Elliott Hughes

riscv64: stop reserving x18 for shadow call stack.

We're switching from x18 to gp, in stages. This change frees up x18
again now bionic and ART have switched to gp. There's no need for a
corresponding "reserve gp" change because gp is automatically reserved.
That's what makes it the perfect choice for shadow call stack (at
least until we get Zsslpcfi and an actual hardware shadow stack pointer
special-purpose register).

Bug: https://github.com/google/android-riscv64/issues/72
Bug: http://b/277909695
Test: treehugger
Change-Id: Iaee1d44cba8daf5d4a27a3791fe3cc28ed1a5d9a

parent f937bad9

cc/config/riscv64_device.go

+0 −4

Original line number	Diff line number	Diff line
		@@ -26,8 +26,6 @@ var (
		// Help catch common 32/64-bit errors.
		"-Werror=implicit-function-declaration",
		"-fno-emulated-tls",
		// For -fsanitize=shadow-call-stack.
		"-ffixed-x18",
		// A temporary fix for SExtWRemoval miscompilation bug.
		"-mllvm",
		"-riscv-disable-sextw-removal=true",
		@@ -37,8 +35,6 @@ var (

		riscv64Ldflags = []string{
		"-Wl,--hash-style=gnu",
		// For -fsanitize=shadow-call-stack.
		"-ffixed-x18",
		}

		riscv64Lldflags = append(riscv64Ldflags,