Merge branch 'omap2-clock' of... (fd9470ce) · Commits · e / devices / samsung / android_kernel_samsung_msm8916

arch/arm/mach-omap2/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,8 @@

		# Common support
		obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
		devices.o serial.o gpmc.o timer-gp.o
		devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
		clockdomain.o

		obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

arch/arm/mach-omap2/clock.c

+42 −4

Original line number	Diff line number	Diff line
		@@ -26,6 +26,7 @@
		#include <asm/io.h>

		#include <mach/clock.h>
		#include <mach/clockdomain.h>
		#include <mach/sram.h>
		#include <mach/cpu.h>
		#include <asm/div64.h>
		@@ -62,9 +63,35 @@
		u8 cpu_mask;

		/*-------------------------------------------------------------------------
		* Omap2 specific clock functions
		* OMAP2/3 specific clock functions
		-------------------------------------------------------------------------/

		/**
		* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
		* @clk: OMAP clock struct ptr to use
		*
		* Convert a clockdomain name stored in a struct clk 'clk' into a
		* clockdomain pointer, and save it into the struct clk. Intended to be
		* called during clk_register(). No return value.
		*/
		void omap2_init_clk_clkdm(struct clk *clk)
		{
		struct clockdomain *clkdm;

		if (!clk->clkdm_name)
		return;

		clkdm = clkdm_lookup(clk->clkdm_name);
		if (clkdm) {
		pr_debug("clock: associated clk %s to clkdm %s\n",
		clk->name, clk->clkdm_name);
		clk->clkdm = clkdm;
		} else {
		pr_debug("clock: could not associate clk %s to "
		"clkdm %s\n", clk->name, clk->clkdm_name);
		}
		}

		/**
		* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
		* @clk: OMAP clock struct ptr to use
		@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk)
		_omap2_clk_disable(clk);
		if (likely((u32)clk->parent))
		omap2_clk_disable(clk->parent);
		if (clk->clkdm)
		omap2_clkdm_clk_disable(clk->clkdm, clk);

		}
		}

		@@ -324,13 +354,21 @@ int omap2_clk_enable(struct clk *clk)
		return ret;
		}

		if (clk->clkdm)
		omap2_clkdm_clk_enable(clk->clkdm, clk);

		ret = _omap2_clk_enable(clk);

		if (unlikely(ret != 0) && clk->parent) {
		if (unlikely(ret != 0)) {
		if (clk->clkdm)
		omap2_clkdm_clk_disable(clk->clkdm, clk);

		if (clk->parent) {
		omap2_clk_disable(clk->parent);
		clk->usecount--;
		}
		}
		}

		return ret;
		}

arch/arm/mach-omap2/clock.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk);
		#endif

		void omap2_clksel_recalc(struct clk *clk);
		void omap2_init_clk_clkdm(struct clk *clk);
		void omap2_init_clksel_parent(struct clk *clk);
		u32 omap2_clksel_get_divisor(struct clk *clk);
		u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

arch/arm/mach-omap2/clock24xx.h

+187 −51

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/clock34xx.c

+20 −11

Original line number	Diff line number	Diff line
		@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
		static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
		{
		const struct dpll_data *dd;
		u32 v;

		dd = clk->dpll_data;

		cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
		dd->control_reg);
		v = __raw_readl(dd->control_reg);
		v &= ~dd->enable_mask;
		v \|= clken_bits << __ffs(dd->enable_mask);
		__raw_writel(v, dd->control_reg);
		}

		/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
		@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
		state <<= dd->idlest_bit;
		idlest_mask = 1 << dd->idlest_bit;

		while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
		while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
		i < MAX_DPLL_WAIT_TRIES) {
		i++;
		udelay(1);
		@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)

		dd = clk->dpll_data;

		v = cm_read_reg(dd->autoidle_reg);
		v = __raw_readl(dd->autoidle_reg);
		v &= dd->autoidle_mask;
		v >>= __ffs(dd->autoidle_mask);

		@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
		static void omap3_dpll_allow_idle(struct clk *clk)
		{
		const struct dpll_data *dd;
		u32 v;

		if (!clk \|\| !clk->dpll_data)
		return;
		@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
		* by writing 0x5 instead of 0x1. Add some mechanism to
		* optionally enter this mode.
		*/
		cm_rmw_reg_bits(dd->autoidle_mask,
		DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
		dd->autoidle_reg);
		v = __raw_readl(dd->autoidle_reg);
		v &= ~dd->autoidle_mask;
		v \|= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
		__raw_writel(v, dd->autoidle_reg);
		}

		/**
		@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
		static void omap3_dpll_deny_idle(struct clk *clk)
		{
		const struct dpll_data *dd;
		u32 v;

		if (!clk \|\| !clk->dpll_data)
		return;

		dd = clk->dpll_data;

		cm_rmw_reg_bits(dd->autoidle_mask,
		DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
		dd->autoidle_reg);
		v = __raw_readl(dd->autoidle_reg);
		v &= ~dd->autoidle_mask;
		v \|= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
		__raw_writel(v, dd->autoidle_reg);
		}

		/* Clock control for DPLL outputs */
		@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
		for (clkp = onchip_34xx_clks;
		clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
		clkp++) {
		if ((*clkp)->flags & cpu_clkflg)
		if ((*clkp)->flags & cpu_clkflg) {
		clk_register(*clkp);
		omap2_init_clk_clkdm(*clkp);
		}
		}

		/* REVISIT: Not yet ready for OMAP3 */