Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fb6f2a6f authored by Alok Kediya's avatar Alok Kediya
Browse files

msm-camera:isp: No wait for stop immediately 



HARD reset of VFE to stop all write masters immediately
for both yuv/bayer.

Change-Id: Ib8999baae8f75498dcc813aa01fbb44f8c104e94
Signed-off-by: default avatarAlok Kediya <kediya@codeaurora.org>
parent 3c59f85d

drivers/media/platform/msm/camera_v2/isp/msm_isp.h

+1 −0
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ struct msm_vfe_stats_shared_data { 
	struct msm_vfe_stats_stream stream_info[MSM_ISP_STATS_MAX];

	uint8_t num_active_stream;

	atomic_t stats_comp_mask[MAX_NUM_STATS_COMP_MASK];

	uint32_t reg_mask;

	uint16_t stream_handle_cnt;

	atomic_t stats_update;

};

drivers/media/platform/msm/camera_v2/isp/msm_isp32.c

+8 −15
Original line number Diff line number Diff line
@@ -366,6 +366,11 @@ static void msm_vfe32_init_hardware_reg(struct vfe_device *vfe_dev) 
	msm_camera_io_w_mb(0x1CFFFFFF, vfe_dev->vfe_base + 0x20);

	msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x24);

	msm_camera_io_w_mb(0x1FFFFFFF, vfe_dev->vfe_base + 0x28);

	msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x6FC);

	msm_camera_io_w(0x10000000, vfe_dev->vfe_base + VFE32_RDI_BASE(1));

	msm_camera_io_w(0x10000000, vfe_dev->vfe_base + VFE32_RDI_BASE(2));

	msm_camera_io_w(0x0, vfe_dev->vfe_base + VFE32_XBAR_BASE(0));

	msm_camera_io_w(0x0, vfe_dev->vfe_base + VFE32_XBAR_BASE(4));



}
@@ -579,7 +584,6 @@ static void msm_vfe32_process_reg_update(struct vfe_device *vfe_dev, 
	uint32_t irq_status0, uint32_t irq_status1,

	struct msm_isp_timestamp *ts)

{

	uint32_t rdi_status;

	uint8_t input_src = 0x0;

	if (!(irq_status0 & 0x20) && !(irq_status1 & 0x1C000000))

		return;
@@ -601,18 +605,6 @@ static void msm_vfe32_process_reg_update(struct vfe_device *vfe_dev, 
		input_src |= (1 << VFE_RAW_2);

	}



	if (vfe_dev->axi_data.stream_update) {

		rdi_status = msm_camera_io_r(vfe_dev->vfe_base +

						VFE32_XBAR_BASE(0));

		rdi_status |= msm_camera_io_r(vfe_dev->vfe_base +

						VFE32_XBAR_BASE(4));



		if (((rdi_status & BIT(7)) || (rdi_status & BIT(7)) ||

			(rdi_status & BIT(7)) || (rdi_status & BIT(7))) &&

			(!(irq_status0 & 0x20)))

			return;

	}



	if (vfe_dev->axi_data.stream_update)

		msm_isp_axi_stream_update(vfe_dev, input_src);

	if (atomic_read(&vfe_dev->stats_data.stats_update))
@@ -648,9 +640,8 @@ static void msm_vfe32_axi_reload_wm( 
		msm_camera_io_w_mb(reload_mask, vfe_dev->vfe_base + 0x38);

	} else {

		/*vfe32 B-family: 8610*/

		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x24);

		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x28);

		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x20);

		msm_camera_io_w(0x1C800000, vfe_dev->vfe_base + 0x20);

		msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x18);

		msm_camera_io_w(0x9AAAAAAA , vfe_dev->vfe_base + 0x600);

		msm_camera_io_w(reload_mask, vfe_dev->vfe_base + 0x38);
@@ -1006,6 +997,8 @@ static void msm_vfe32_axi_clear_wm_reg( 
{

	uint32_t val = 0;

	uint32_t wm_base = VFE32_WM_BASE(stream_info->wm[plane_idx]);

	/* FRAME BASED */

	msm_camera_io_w(val, vfe_dev->vfe_base + wm_base);

	/*WR_IMAGE_SIZE*/

	msm_camera_io_w(val, vfe_dev->vfe_base + wm_base + 0x10);

	/*WR_BUFFER_CFG*/

drivers/media/platform/msm/camera_v2/isp/msm_isp40.c

+11 −7
Original line number Diff line number Diff line
@@ -402,6 +402,8 @@ static void msm_vfe40_init_hardware_reg(struct vfe_device *vfe_dev) 
	msm_camera_io_w(0, vfe_dev->vfe_base + 0x30);

	msm_camera_io_w_mb(0, vfe_dev->vfe_base + 0x34);

	msm_camera_io_w(1, vfe_dev->vfe_base + 0x24);

	msm_camera_io_w(vfe_dev->stats_data.reg_mask,

		vfe_dev->vfe_base + 0x44);

}



static void msm_vfe40_clear_status_reg(struct vfe_device *vfe_dev)
@@ -1452,7 +1454,7 @@ static int msm_vfe40_stats_check_streams( 
static void msm_vfe40_stats_cfg_comp_mask(struct vfe_device *vfe_dev,

	uint32_t stats_mask, uint8_t enable)

{

	uint32_t reg_mask, comp_stats_mask;

	uint32_t comp_stats_mask;

	uint32_t i = 0;

	atomic_t *stats_comp;

	struct msm_vfe_stats_shared_data *stats_data = &vfe_dev->stats_data;
@@ -1471,15 +1473,17 @@ static void msm_vfe40_stats_cfg_comp_mask(struct vfe_device *vfe_dev, 
	for (i = 0;

		i < vfe_dev->hw_info->stats_hw_info->num_stats_comp_mask; i++) {



		reg_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x44);

		comp_stats_mask = reg_mask & (STATS_COMP_BIT_MASK << (i*8));

		stats_data->reg_mask =

		  msm_camera_io_r(vfe_dev->vfe_base + 0x44);

		comp_stats_mask =

		  stats_data->reg_mask & (STATS_COMP_BIT_MASK << (i*8));

		stats_comp = &stats_data->stats_comp_mask[i];



		if (enable) {

			if (comp_stats_mask)

				continue;



			reg_mask |= (stats_mask << (16 + i*8));

			stats_data->reg_mask |= (stats_mask << (16 + i*8));

			atomic_add(stats_mask, stats_comp);

		} else {

			/*
@@ -1492,13 +1496,13 @@ static void msm_vfe40_stats_cfg_comp_mask(struct vfe_device *vfe_dev, 
				continue;



			atomic_sub(stats_mask, stats_comp);

			reg_mask &= ~(stats_mask << (16 + i*8));

			stats_data->reg_mask &= ~(stats_mask << (16 + i*8));

		}

		ISP_DBG("%s: comp_mask: %x atomic stats[0]: %x %x\n",

			__func__, reg_mask,

			__func__, stats_data->reg_mask,

			atomic_read(&stats_data->stats_comp_mask[0]),

			atomic_read(&stats_data->stats_comp_mask[1]));

		msm_camera_io_w(reg_mask, vfe_dev->vfe_base + 0x44);

		msm_camera_io_w(stats_data->reg_mask, vfe_dev->vfe_base + 0x44);

		return;

	}

}

drivers/media/platform/msm/camera_v2/isp/msm_isp44.c

+11 −7
Original line number Diff line number Diff line
@@ -255,6 +255,8 @@ static void msm_vfe44_init_hardware_reg(struct vfe_device *vfe_dev) 
	msm_camera_io_w_mb(0xFFFFFFFF, vfe_dev->vfe_base + 0x2C);

	msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x30);

	msm_camera_io_w_mb(0xFFFFFFFF, vfe_dev->vfe_base + 0x34);

	msm_camera_io_w(vfe_dev->stats_data.reg_mask,

		vfe_dev->vfe_base + 0x44);

}



static void msm_vfe44_clear_status_reg(struct vfe_device *vfe_dev)
@@ -1408,7 +1410,7 @@ static void msm_vfe44_stats_cfg_comp_mask( 
	struct vfe_device *vfe_dev,

	uint32_t stats_mask, uint8_t enable)

{

	uint32_t reg_mask, comp_stats_mask, mask_bf_scale;

	uint32_t comp_stats_mask, mask_bf_scale;

	uint32_t i = 0;

	atomic_t *stats_comp;

	struct msm_vfe_stats_shared_data *stats_data = &vfe_dev->stats_data;
@@ -1434,14 +1436,16 @@ static void msm_vfe44_stats_cfg_comp_mask( 
	for (i = 0;

		i < vfe_dev->hw_info->stats_hw_info->num_stats_comp_mask; i++) {

		stats_comp = &stats_data->stats_comp_mask[i];

		reg_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x44);

		comp_stats_mask = reg_mask & (STATS_COMP_BIT_MASK << (i*8));

		stats_data->reg_mask =

		  msm_camera_io_r(vfe_dev->vfe_base + 0x44);

		comp_stats_mask =

		  stats_data->reg_mask & (STATS_COMP_BIT_MASK << (i*8));



		if (enable) {

			if (comp_stats_mask)

				continue;



			reg_mask |= (mask_bf_scale << (16 + i*8));

			stats_data->reg_mask |= (mask_bf_scale << (16 + i*8));

			atomic_set(stats_comp, stats_mask |

					atomic_read(stats_comp));

			break;
@@ -1459,17 +1463,17 @@ static void msm_vfe44_stats_cfg_comp_mask( 


			atomic_set(stats_comp,

					~stats_mask & atomic_read(stats_comp));

			reg_mask &= ~(mask_bf_scale << (16 + i*8));

			stats_data->reg_mask &= ~(mask_bf_scale << (16 + i*8));

			break;

		}

	}



	ISP_DBG("%s: comp_mask: %x atomic stats[0]: %x %x\n",

		__func__, reg_mask,

		__func__, stats_data->reg_mask,

		atomic_read(&stats_data->stats_comp_mask[0]),

		atomic_read(&stats_data->stats_comp_mask[1]));



	msm_camera_io_w(reg_mask, vfe_dev->vfe_base + 0x44);

	msm_camera_io_w(stats_data->reg_mask, vfe_dev->vfe_base + 0x44);

	return;

}

drivers/media/platform/msm/camera_v2/isp/msm_isp46.c

+11 −7
Original line number Diff line number Diff line
@@ -293,6 +293,8 @@ static void msm_vfe46_init_hardware_reg(struct vfe_device *vfe_dev) 
	msm_camera_io_w_mb(0xE1FFFFFF, vfe_dev->vfe_base + 0x60);

	msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x64);

	msm_camera_io_w_mb(0xFFFFFFFF, vfe_dev->vfe_base + 0x68);

	msm_camera_io_w(vfe_dev->stats_data.reg_mask,

		vfe_dev->vfe_base + 0x78);

}



static void msm_vfe46_clear_status_reg(struct vfe_device *vfe_dev)
@@ -1382,7 +1384,7 @@ static void msm_vfe46_stats_cfg_comp_mask( 
	struct vfe_device *vfe_dev,

	uint32_t stats_mask, uint8_t enable)

{

	uint32_t reg_mask, comp_stats_mask, mask_bf_scale;

	uint32_t comp_stats_mask, mask_bf_scale;

	uint32_t i = 0;

	atomic_t *stats_comp;

	struct msm_vfe_stats_shared_data *stats_data = &vfe_dev->stats_data;
@@ -1408,14 +1410,16 @@ static void msm_vfe46_stats_cfg_comp_mask( 
	for (i = 0;

		i < vfe_dev->hw_info->stats_hw_info->num_stats_comp_mask; i++) {

		stats_comp = &stats_data->stats_comp_mask[i];

		reg_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x78);

		comp_stats_mask = reg_mask & (STATS_COMP_BIT_MASK << (i*8));

		stats_data->reg_mask =

		  msm_camera_io_r(vfe_dev->vfe_base + 0x78);

		comp_stats_mask =

		  stats_data->reg_mask & (STATS_COMP_BIT_MASK << (i*8));



		if (enable) {

			if (comp_stats_mask)

				continue;



			reg_mask |= (mask_bf_scale << (16 + i*8));

			stats_data->reg_mask |= (mask_bf_scale << (16 + i*8));

			atomic_set(stats_comp, stats_mask |

					atomic_read(stats_comp));

			break;
@@ -1433,17 +1437,17 @@ static void msm_vfe46_stats_cfg_comp_mask( 


			atomic_set(stats_comp,

					~stats_mask & atomic_read(stats_comp));

			reg_mask &= ~(mask_bf_scale << (16 + i*8));

			stats_data->reg_mask &= ~(mask_bf_scale << (16 + i*8));

			break;

		}

	}



	ISP_DBG("%s: comp_mask: %x atomic stats[0]: %x %x\n",

		__func__, reg_mask,

		__func__, stats_data->reg_mask,

		atomic_read(&stats_data->stats_comp_mask[0]),

		atomic_read(&stats_data->stats_comp_mask[1]));



	msm_camera_io_w(reg_mask, vfe_dev->vfe_base + 0x78);

	msm_camera_io_w(stats_data->reg_mask, vfe_dev->vfe_base + 0x78);

	return;

}