Loading Documentation/devicetree/bindings/pci/msm_pcie.txt +3 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,8 @@ Optional Properties: - qcom,msi-gicm-addr: MSI address for GICv2m. - qcom,msi-gicm-base: MSI IRQ base for GICv2m. - qcom,ext-ref-clk: The reference clock is external. - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become stable after power on, before de-assert the PERST to the endpoint. Example: Loading Loading @@ -113,4 +115,5 @@ Example: qcom,msi-gicm-addr = <0xf9040040>; qcom,msi-gicm-base = <0x160>; qcom,ext-ref-clk; qcom,ep-latency = <100>; }; arch/arm/mach-msm/pcie.c +13 −0 Original line number Diff line number Diff line Loading @@ -963,6 +963,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) goto link_fail; } if (dev->ep_latency) msleep(dev->ep_latency); /* de-assert PCIe reset link to bring EP out of reset */ pr_info("PCIe: Release the reset of endpoint\n"); Loading Loading @@ -1247,6 +1250,16 @@ static int msm_pcie_probe(struct platform_device *pdev) PCIE_DBG("ref clk is %s.\n", msm_pcie_dev[rc_idx].ext_ref_clk ? "external" : "internal"); msm_pcie_dev[rc_idx].ep_latency = 0; ret = of_property_read_u32((&pdev->dev)->of_node, "qcom,ep-latency", &msm_pcie_dev[rc_idx].ep_latency); if (ret) PCIE_DBG("ep-latency does not exist.\n"); else PCIE_DBG("ep-latency: 0x%x.\n", msm_pcie_dev[rc_idx].ep_latency); msm_pcie_dev[rc_idx].msi_gicm_addr = 0; msm_pcie_dev[rc_idx].msi_gicm_base = 0; ret = of_property_read_u32((&pdev->dev)->of_node, Loading arch/arm/mach-msm/pcie.h +1 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,7 @@ struct msm_pcie_dev_t { bool l1ss_supported; bool aux_clk_sync; bool ext_ref_clk; uint32_t ep_latency; uint32_t rc_idx; bool enumerated; Loading Loading
Documentation/devicetree/bindings/pci/msm_pcie.txt +3 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,8 @@ Optional Properties: - qcom,msi-gicm-addr: MSI address for GICv2m. - qcom,msi-gicm-base: MSI IRQ base for GICv2m. - qcom,ext-ref-clk: The reference clock is external. - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become stable after power on, before de-assert the PERST to the endpoint. Example: Loading Loading @@ -113,4 +115,5 @@ Example: qcom,msi-gicm-addr = <0xf9040040>; qcom,msi-gicm-base = <0x160>; qcom,ext-ref-clk; qcom,ep-latency = <100>; };
arch/arm/mach-msm/pcie.c +13 −0 Original line number Diff line number Diff line Loading @@ -963,6 +963,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) goto link_fail; } if (dev->ep_latency) msleep(dev->ep_latency); /* de-assert PCIe reset link to bring EP out of reset */ pr_info("PCIe: Release the reset of endpoint\n"); Loading Loading @@ -1247,6 +1250,16 @@ static int msm_pcie_probe(struct platform_device *pdev) PCIE_DBG("ref clk is %s.\n", msm_pcie_dev[rc_idx].ext_ref_clk ? "external" : "internal"); msm_pcie_dev[rc_idx].ep_latency = 0; ret = of_property_read_u32((&pdev->dev)->of_node, "qcom,ep-latency", &msm_pcie_dev[rc_idx].ep_latency); if (ret) PCIE_DBG("ep-latency does not exist.\n"); else PCIE_DBG("ep-latency: 0x%x.\n", msm_pcie_dev[rc_idx].ep_latency); msm_pcie_dev[rc_idx].msi_gicm_addr = 0; msm_pcie_dev[rc_idx].msi_gicm_base = 0; ret = of_property_read_u32((&pdev->dev)->of_node, Loading
arch/arm/mach-msm/pcie.h +1 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,7 @@ struct msm_pcie_dev_t { bool l1ss_supported; bool aux_clk_sync; bool ext_ref_clk; uint32_t ep_latency; uint32_t rc_idx; bool enumerated; Loading