microblaze_v8: Interrupt handling and timer support

/*

 * Copyright (C) 2006 Atmark Techno, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License. See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef _ASM_MICROBLAZE_IRQ_H

#define _ASM_MICROBLAZE_IRQ_H

#define NR_IRQS 32

#include <linux/interrupt.h>

extern unsigned int nr_irq;

#define NO_IRQ (-1)

static inline int irq_canonicalize(int irq)

{

	return irq;

}

struct pt_regs;

extern void do_IRQ(struct pt_regs *regs);

/* irq_of_parse_and_map - Parse and Map an interrupt into linux virq space

 * @device: Device node of the device whose interrupt is to be mapped

 * @index: Index of the interrupt to map

 *

 * This function is a wrapper that chains of_irq_map_one() and

 * irq_create_of_mapping() to make things easier to callers

 */

struct device_node;

extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);

/** FIXME - not implement

 * irq_dispose_mapping - Unmap an interrupt

 * @virq: linux virq number of the interrupt to unmap

 */

static inline void irq_dispose_mapping(unsigned int virq)

{

	return;

}

#endif /* _ASM_MICROBLAZE_IRQ_H */

/*

 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>

 * Copyright (C) 2007-2009 PetaLogix

 * Copyright (C) 2006 Atmark Techno, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License. See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/init.h>

#include <linux/irq.h>

#include <asm/page.h>

#include <linux/io.h>

#include <asm/prom.h>

#include <asm/irq.h>

#ifdef CONFIG_SELFMOD_INTC

#include <asm/selfmod.h>

#define INTC_BASE	BARRIER_BASE_ADDR

#else

static unsigned int intc_baseaddr;

#define INTC_BASE	intc_baseaddr

#endif

unsigned int nr_irq;

/* No one else should require these constants, so define them locally here. */

#define ISR 0x00			/* Interrupt Status Register */

#define IPR 0x04			/* Interrupt Pending Register */

#define IER 0x08			/* Interrupt Enable Register */

#define IAR 0x0c			/* Interrupt Acknowledge Register */

#define SIE 0x10			/* Set Interrupt Enable bits */

#define CIE 0x14			/* Clear Interrupt Enable bits */

#define IVR 0x18			/* Interrupt Vector Register */

#define MER 0x1c			/* Master Enable Register */

#define MER_ME (1<<0)

#define MER_HIE (1<<1)

static void intc_enable_or_unmask(unsigned int irq)

{

	pr_debug("enable_or_unmask: %d\n", irq);

	out_be32(INTC_BASE + SIE, 1 << irq);

}

static void intc_disable_or_mask(unsigned int irq)

{

	pr_debug("disable: %d\n", irq);

	out_be32(INTC_BASE + CIE, 1 << irq);

}

static void intc_ack(unsigned int irq)

{

	pr_debug("ack: %d\n", irq);

	out_be32(INTC_BASE + IAR, 1 << irq);

}

static void intc_mask_ack(unsigned int irq)

{

	unsigned long mask = 1 << irq;

	pr_debug("disable_and_ack: %d\n", irq);

	out_be32(INTC_BASE + CIE, mask);

	out_be32(INTC_BASE + IAR, mask);

}

static void intc_end(unsigned int irq)

{

	unsigned long mask = 1 << irq;

	pr_debug("end: %d\n", irq);

	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {

		out_be32(INTC_BASE + SIE, mask);

		/* ack level sensitive intr */

		if (irq_desc[irq].status & IRQ_LEVEL)

			out_be32(INTC_BASE + IAR, mask);

	}

}

static struct irq_chip intc_dev = {

	.name = "Xilinx INTC",

	.unmask = intc_enable_or_unmask,

	.mask = intc_disable_or_mask,

	.ack = intc_ack,

	.mask_ack = intc_mask_ack,

	.end = intc_end,

};

unsigned int get_irq(struct pt_regs *regs)

{

	int irq;

	/*

	 * NOTE: This function is the one that needs to be improved in

	 * order to handle multiple interrupt controllers. It currently

	 * is hardcoded to check for interrupts only on the first INTC.

	 */

	irq = in_be32(INTC_BASE + IVR);

	pr_debug("get_irq: %d\n", irq);

	return irq;

}

void __init init_IRQ(void)

{

	u32 i, j, intr_type;

	struct device_node *intc = NULL;

#ifdef CONFIG_SELFMOD_INTC

	unsigned int intc_baseaddr = 0;

	static int arr_func[] = {

				(int)&get_irq,

				(int)&intc_enable_or_unmask,

				(int)&intc_disable_or_mask,

				(int)&intc_mask_ack,

				(int)&intc_ack,

				(int)&intc_end,

				0

			};

#endif

	static char *intc_list[] = {

				"xlnx,xps-intc-1.00.a",

				"xlnx,opb-intc-1.00.c",

				"xlnx,opb-intc-1.00.b",

				"xlnx,opb-intc-1.00.a",

				NULL

			};

	for (j = 0; intc_list[j] != NULL; j++) {

		intc = of_find_compatible_node(NULL, NULL, intc_list[j]);

		if (intc)

			break;

	}

	intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);

	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);

	nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL);

	intr_type =

		*(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL);

	if (intr_type >= (1 << nr_irq))

		printk(KERN_INFO " ERROR: Mishmash in king-of-intr param\n");

#ifdef CONFIG_SELFMOD_INTC

	selfmod_function((int *) arr_func, intc_baseaddr);

#endif

	printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",

		intc_list[j], intc_baseaddr, nr_irq, intr_type);

	/*

	 * Disable all external interrupts until they are

	 * explicity requested.

	 */

	out_be32(intc_baseaddr + IER, 0);

	/* Acknowledge any pending interrupts just in case. */

	out_be32(intc_baseaddr + IAR, 0xffffffff);

	/* Turn on the Master Enable. */

	out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);

	for (i = 0; i < nr_irq; ++i) {

		if (intr_type & (0x00000001 << i)) {

			set_irq_chip_and_handler_name(i, &intc_dev,

				handle_edge_irq, intc_dev.name);

			irq_desc[i].status &= ~IRQ_LEVEL;

		} else {

			set_irq_chip_and_handler_name(i, &intc_dev,

				handle_level_irq, intc_dev.name);

			irq_desc[i].status |= IRQ_LEVEL;

		}

	}

}

/*

 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>

 * Copyright (C) 2007-2009 PetaLogix

 * Copyright (C) 2006 Atmark Techno, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License. See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/hardirq.h>

#include <linux/interrupt.h>

#include <linux/irqflags.h>

#include <linux/seq_file.h>

#include <linux/kernel_stat.h>

#include <linux/irq.h>

#include <asm/prom.h>

unsigned int irq_of_parse_and_map(struct device_node *dev, int index)

{

	struct of_irq oirq;

	if (of_irq_map_one(dev, index, &oirq))

		return NO_IRQ;

	return oirq.specifier[0];

}

EXPORT_SYMBOL_GPL(irq_of_parse_and_map);

/*

 * 'what should we do if we get a hw irq event on an illegal vector'.

 * each architecture has to answer this themselves.

 */

void ack_bad_irq(unsigned int irq)

{

	printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);

}

static u32 concurrent_irq;

void do_IRQ(struct pt_regs *regs)

{

	unsigned int irq;

	struct pt_regs *old_regs = set_irq_regs(regs);

	irq_enter();

	irq = get_irq(regs);

next_irq:

	BUG_ON(irq == -1U);

	generic_handle_irq(irq);

	irq = get_irq(regs);

	if (irq != -1U) {

		pr_debug("next irq: %d\n", irq);

		++concurrent_irq;

		goto next_irq;

	}

	irq_exit();

	set_irq_regs(old_regs);

}

int show_interrupts(struct seq_file *p, void *v)

{

	int i = *(loff_t *) v, j;

	struct irqaction *action;

	unsigned long flags;

	if (i == 0) {

		seq_printf(p, "		");

		for_each_online_cpu(j)

			seq_printf(p, "CPU%-8d", j);

		seq_putc(p, '\n');

	}

	if (i < nr_irq) {

		spin_lock_irqsave(&irq_desc[i].lock, flags);

		action = irq_desc[i].action;

		if (!action)

			goto skip;

		seq_printf(p, "%3d: ", i);

#ifndef CONFIG_SMP

		seq_printf(p, "%10u ", kstat_irqs(i));

#else

		for_each_online_cpu(j)

			seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);

#endif

		seq_printf(p, " %8s", irq_desc[i].status &

					IRQ_LEVEL ? "level" : "edge");

		seq_printf(p, " %8s", irq_desc[i].chip->name);

		seq_printf(p, "  %s", action->name);

		for (action = action->next; action; action = action->next)

			seq_printf(p, ", %s", action->name);

		seq_putc(p, '\n');

skip:

		spin_unlock_irqrestore(&irq_desc[i].lock, flags);

	}

	return 0;

}

/*

 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>

 * Copyright (C) 2007-2009 PetaLogix

 * Copyright (C) 2006 Atmark Techno, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License. See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/param.h>

#include <linux/interrupt.h>

#include <linux/profile.h>

#include <linux/irq.h>

#include <linux/delay.h>

#include <linux/sched.h>

#include <linux/spinlock.h>

#include <linux/err.h>

#include <linux/clk.h>

#include <linux/clocksource.h>

#include <linux/clockchips.h>

#include <linux/io.h>

#include <asm/cpuinfo.h>

#include <asm/setup.h>

#include <asm/prom.h>

#include <asm/irq.h>

#include <asm/system.h>

#ifdef CONFIG_SELFMOD_TIMER

#include <asm/selfmod.h>

#define TIMER_BASE	BARRIER_BASE_ADDR

#else

static unsigned int timer_baseaddr;

#define TIMER_BASE	timer_baseaddr

#endif

#define TCSR0	(0x00)

#define TLR0	(0x04)

#define TCR0	(0x08)

#define TCSR1	(0x10)

#define TLR1	(0x14)

#define TCR1	(0x18)

#define TCSR_MDT	(1<<0)

#define TCSR_UDT	(1<<1)

#define TCSR_GENT	(1<<2)

#define TCSR_CAPT	(1<<3)

#define TCSR_ARHT	(1<<4)

#define TCSR_LOAD	(1<<5)

#define TCSR_ENIT	(1<<6)

#define TCSR_ENT	(1<<7)

#define TCSR_TINT	(1<<8)

#define TCSR_PWMA	(1<<9)

#define TCSR_ENALL	(1<<10)

static inline void microblaze_timer0_stop(void)

{

	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);

}

static inline void microblaze_timer0_start_periodic(unsigned long load_val)

{

	if (!load_val)

		load_val = 1;

	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */

	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	/* see timer data sheet for detail

	 * !ENALL - don't enable 'em all

	 * !PWMA - disable pwm

	 * TINT - clear interrupt status

	 * ENT- enable timer itself

	 * EINT - enable interrupt

	 * !LOAD - clear the bit to let go

	 * ARHT - auto reload

	 * !CAPT - no external trigger

	 * !GENT - no external signal

	 * UDT - set the timer as down counter

	 * !MDT0 - generate mode

	 */

	out_be32(TIMER_BASE + TCSR0,

			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);

}

static inline void microblaze_timer0_start_oneshot(unsigned long load_val)

{

	if (!load_val)

		load_val = 1;

	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */

	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	out_be32(TIMER_BASE + TCSR0,

			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);

}

static int microblaze_timer_set_next_event(unsigned long delta,

					struct clock_event_device *dev)

{

	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);

	microblaze_timer0_start_oneshot(delta);

	return 0;

}

static void microblaze_timer_set_mode(enum clock_event_mode mode,

				struct clock_event_device *evt)

{

	switch (mode) {

	case CLOCK_EVT_MODE_PERIODIC:

		printk(KERN_INFO "%s: periodic\n", __func__);

		microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);

		break;

	case CLOCK_EVT_MODE_ONESHOT:

		printk(KERN_INFO "%s: oneshot\n", __func__);

		break;

	case CLOCK_EVT_MODE_UNUSED:

		printk(KERN_INFO "%s: unused\n", __func__);

		break;

	case CLOCK_EVT_MODE_SHUTDOWN:

		printk(KERN_INFO "%s: shutdown\n", __func__);

		microblaze_timer0_stop();

		break;

	case CLOCK_EVT_MODE_RESUME:

		printk(KERN_INFO "%s: resume\n", __func__);

		break;

	}

}

static struct clock_event_device clockevent_microblaze_timer = {

	.name		= "microblaze_clockevent",

	.features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,

	.shift		= 24,

	.rating		= 300,

	.set_next_event	= microblaze_timer_set_next_event,

	.set_mode	= microblaze_timer_set_mode,

};

static inline void timer_ack(void)

{

	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));

}

static irqreturn_t timer_interrupt(int irq, void *dev_id)

{

	struct clock_event_device *evt = &clockevent_microblaze_timer;

#ifdef CONFIG_HEART_BEAT

	heartbeat();

#endif

	timer_ack();

	evt->event_handler(evt);

	return IRQ_HANDLED;

}

static struct irqaction timer_irqaction = {

	.handler = timer_interrupt,

	.flags = IRQF_DISABLED | IRQF_TIMER,

	.name = "timer",

	.dev_id = &clockevent_microblaze_timer,

};

static __init void microblaze_clockevent_init(void)

{

	clockevent_microblaze_timer.mult =

		div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,

				clockevent_microblaze_timer.shift);

	clockevent_microblaze_timer.max_delta_ns =

		clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);

	clockevent_microblaze_timer.min_delta_ns =

		clockevent_delta2ns(1, &clockevent_microblaze_timer);

	clockevent_microblaze_timer.cpumask = cpumask_of(0);

	clockevents_register_device(&clockevent_microblaze_timer);

}

static cycle_t microblaze_read(void)

{

	/* reading actual value of timer 1 */

	return (cycle_t) (in_be32(TIMER_BASE + TCR1));

}

static struct clocksource clocksource_microblaze = {

	.name		= "microblaze_clocksource",

	.rating		= 300,

	.read		= microblaze_read,

	.mask		= CLOCKSOURCE_MASK(32),

	.shift		= 24, /* I can shift it */

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};

static int __init microblaze_clocksource_init(void)

{

	clocksource_microblaze.mult =

			clocksource_hz2mult(cpuinfo.cpu_clock_freq,

						clocksource_microblaze.shift);

	if (clocksource_register(&clocksource_microblaze))

		panic("failed to register clocksource");

	/* stop timer1 */

	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);

	/* start timer1 - up counting without interrupt */

	out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);

	return 0;

}

void __init time_init(void)

{

	u32 irq, i = 0;

	u32 timer_num = 1;

	struct device_node *timer = NULL;

#ifdef CONFIG_SELFMOD_TIMER

	unsigned int timer_baseaddr = 0;

	int arr_func[] = {

				(int)&microblaze_read,

				(int)&timer_interrupt,

				(int)&microblaze_clocksource_init,

				(int)&microblaze_timer_set_mode,

				(int)&microblaze_timer_set_next_event,

				0

			};

#endif

	char *timer_list[] = {

				"xlnx,xps-timer-1.00.a",

				"xlnx,opb-timer-1.00.b",

				"xlnx,opb-timer-1.00.a",

				NULL

			};

	for (i = 0; timer_list[i] != NULL; i++) {

		timer = of_find_compatible_node(NULL, NULL, timer_list[i]);

		if (timer)

			break;

	}

	timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);

	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);

	irq = *(int *) of_get_property(timer, "interrupts", NULL);

	timer_num =

		*(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);

	if (timer_num) {

		printk(KERN_EMERG "Please enable two timers in HW\n");

		BUG();

	}

#ifdef CONFIG_SELFMOD_TIMER

	selfmod_function((int *) arr_func, timer_baseaddr);

#endif

	printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",

		timer_list[i], timer_baseaddr, irq);

	cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;

	setup_irq(irq, &timer_irqaction);

#ifdef CONFIG_HEART_BEAT

	setup_heartbeat();

#endif

	microblaze_clocksource_init();

	microblaze_clockevent_init();

}